tag: IP

The Multiplier And The Singularity
By Brian Bailey - 12 Jan, 2017 - Comments: 8

In 1993, Vernor Vinge, a computer scientist and science fiction writer, first described an event called the Singularity—the point when machine intelligence matches and then surpasses human intelligence. And since then, top scientists, engineers and futurists have been asking just how far away we are from that event. In 2006, Ray Kurzweil published a book, "The Singularity is Near," in whic... » read more

IoT Will Grow Faster With More Flexible Wireless Design
By Prithi Ramakrishnan - 12 Jan, 2017 - Comments: 0

The fascinating numbers-within-the-numbers for the forecasted growth in Internet of Things (IoT) devices is this: By 2020, it’s estimated there will be nearly 2 billion low-power radio-connected devices, specifically with Bluetooth 5 and 802.15.4 (Zigbee and Thread). Those numbers are compelling because not only is that a quadrupling of the amount of low-power radio devices today, but the val... » read more

How A Complete IP Solution Speeds Time-to-Market And Reduces Risk For 10 Gigabit Ethernet Applications
By Synopsys - 11 Jan, 2017 - Comments: 0

This paper discusses the merits of IP for the growing 10G Ethernet market and introduces Synopsys’ complete DesignWare 10G Ethernet IP solution in the context of the technology and the target market. To read more, click here. » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Tech Talk: Timing Closure
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

EDA, IP Up 7%
By Ed Sperling - 22 Dec, 2016 - Comments: 0

EDA and IP growth increased to $2.094 billion in Q3, a 7% gain over the $1.958 billion reported for the same period in 2015, according to just released data from the Electronic System Design Alliance Market Statistics Service. All geographic regions reported growth last quarter. So did computer-aided engineering, the largest single category, which grew 5.0% to $666.7 million in Q3, up from $... » read more

Tools For Heterogeneous System Development
By Brian Bailey - 22 Dec, 2016 - Comments: 1

System architects look to both heterogeneous and homogeneous computing when there are no other options available, but the current thinking is that a system-level software methodology could simplify the design, ease integration of various blocks, and potentially improve performance for less power. While the theory appears sound enough, implementing it has turned out to be harder than expected. ... » read more

Formal’s Roadmap
By Brian Bailey - 12 Dec, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

IP Liability Changes Ahead?
By Ed Sperling - 08 Dec, 2016 - Comments: 0

Patent lawyers are keeping close tabs on a biotech patent infringement case that went before the Supreme Court this week because it could have a significant impact on IP content in other markets, including semiconductors. On Tuesday, attorneys for Life Technologies Corp. and Promega Corp., presented arguments before the U.S. Supreme Court involving an enzyme for amplifying DNA analysis. For ... » read more

How High-Level Synthesis Was Used to Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 07 Dec, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

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