Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Making 2.5D, Fan-Outs Cheaper


Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

Teaching Computers To See


Vision processing is emerging as a foundation technology for a number of high-growth applications, spurring a wave of intensive research to reduce power, improve performance, and push embedded vision into the mainstream to leverage economies of scale. What began as a relatively modest development effort has turned into an all-out race for a piece of this market, and for good reason. Mark... » read more

Partitioning For Power


Examine any smartphone design today and most of the electronic circuitry is "off" most of the time. And regardless of how many processor cores are available, it's rare to use more than a couple of those cores at any point in time. The emphasis is shifting, though, as the mobility market flattens and other markets such as driver-assisted vehicles and IoT begin gaining traction. In a car, turn... » read more

Politics And (Low) Power


This week the entire semiconductor market woke up with a severe political hangover. Aside from the initial shock of the election results themselves, the winning platform of "America First" could have far-reaching implications for an industry that has spent decades optimizing a global supply chain the way it has finely tuned other processes to reduce the cost per transistor. There are many un... » read more

Three Power-Saving Techniques Using PCI Express IP


The increasing data traffic between devices in a computing application environment is causing a large power footprint, and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to s... » read more

Making Mobile Payments Simple


The origins of commerce can be traced back to prehistoric times when early civilizations bartered goods and services. Although the introduction of currency in various forms marked a critical milestone for commerce, very little has actually changed since the early days of open-air markets. Plastic may have replaced paper, yet fundamentally, the brick-and-mortar experience has remained static for... » read more

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP


The proposed IEEE 802.11ah wireless networking protocol is designed to meet the requirements of Internet of Things (IoT) connectivity, providing the bit rate, security, and low power required for these types of connected devices. Design requirements for 802.11ah access point and clients vary widely, even though all implement the same mathematical algorithm. In this paper, we will discuss how... » read more

Is Security All Talk?


Security is the No. 1 recurring theme at conferences these days. And given the explosion in the number of conferences this year—up to a half dozen some weeks just in Silicon Valley—that's a lot of attention being showered on security. At nearly all of these talks, there is at least a mention about recent breaches, pervasive and persistent risks, and the growing threat level. The topic of... » read more

Gaps In The Verification Flow


Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

← Older posts Newer posts →