tag: Intel

Co-Packaged Optics Reaches Power Efficiency Tipping Point
By Laura Peters - 02 Jun, 2025 - Comments: 0

Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Chip Industry Week in Review
By The SE Staff - 23 May, 2025 - Comments: 0

Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Advanced Packaging Depends On Materials And Co-Design
By Katherine Derbyshire - 22 May, 2025 - Comments: 0

Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch. Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine com... » read more

Chip Industry Technical Paper Roundup: May 20
By Linda Christensen - 20 May, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=432 /] Find more semiconductor research papers here. » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Chip Industry Week in Review
By The SE Staff - 09 May, 2025 - Comments: 0

Check out the Inside Chips podcast for our behind-the-scenes analysis. The U.S. government is rescinding a Biden-era AI export rule that would have imposed complex restrictions on how U.S. chip and AI technology is sold abroad, a move welcomed by companies like Nvidia, reports Bloomberg. While new, simpler guidelines are expected in the coming months, the decision introduces short-term uncer... » read more

Chip Industry Week in Review
By The SE Staff - 02 May, 2025 - Comments: 0

Check out the Inside Chips podcast for our behind-the-scenes analysis of changes at Intel Foundry. Intel rolled out its updated process technology roadmap this week, along with early process design kit (PDK) for its 14A gate-all-around process technology. That node will utilize high-NA EUV, and include direct contact power delivery, the second generation of its backside power delivery techno... » read more

Chip Industry Week In Review
By The SE Staff - 18 Apr, 2025 - Comments: 0

[Podcast version is here.] TSMC said it will produce 30% of its leading-edge chips in Arizona when all six of its fabs are operational, a total investment of $165 billion, Axios reported. In its latest SEC filing, the foundry said it continues to add capacity in Taiwan, Arizona, Japan, and Germany. The Trump administration launched a Section 232 investigation into semiconductors and relat... » read more

Backside Power Delivery Nears Production
By Laura Peters - 17 Apr, 2025 - Comments: 0

Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling. It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern di... » read more

2030 Data Center AI Chip Winners: The Trillion Dollar Club
By Geoff Tate - 07 Apr, 2025 - Comments: 0

At the start of 2025, I believed AI was overhyped, ASICs were a niche, and a market pullback was inevitable. My long-term view has changed dramatically. AI technology and adoption is accelerating at an astonishing pace. One of the GenAI/LLM leaders, or Nvidia, will be the first $10 Trillion market cap company by 2030. Large language models (LLMs) are rapidly improving in both capability and ... » read more

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