tag: Intel

Chip Industry Week In Review
By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Chip Industry Week In Review
By The SE Staff - 28 Feb, 2025 - Comments: 0

Intel said its new fab in Licking County, Ohio will be delayed due to financial struggles and a need to align chip production with market demand, reported the Columbus Dispatch. Construction is now estimated to be completed in 2030, with operations to start in 2030 or 2031. The company said it already has invested $3.7 billion locally. Apple plans to invest more than $500 billion in the U.S... » read more

Chip Industry Week In Review
By The SE Staff - 21 Feb, 2025 - Comments: 0

The EU Commission approved €920 million in German State aid to support Infineon in setting up its Smart Power Fab in Dresden. Total funding for the Dresden site amounts to about €1 billion. PDF Solutions will acquire secureWISE for $130 million to expand the reach of its semiconductor manufacturing data platform, providing secure, remote access monitoring and control. Tariffs, trade, and ... » read more

Interconnects Approach Tipping Point
By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

EUV’s Future Looks Even Brighter
By Gregory Haley - 20 Feb, 2025 - Comments: 1

The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry's ability to meet demand. The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on ... » read more

Universities Augment Engineering Curricula To Boost Employability
By Liz Allan - 05 Feb, 2025 - Comments: 0

Increasing numbers of universities are offering semiconductor courses in their engineering programs, and also in math, physics, and business degrees. Most universities now offer a broad foundation so students can pivot to other industries during cyclical downturns, or when technology and science create entirely new and potentially lucrative opportunities, such as generative AI, advanced pack... » read more

Chip Industry Technical Paper Roundup: Feb. 4
By Linda Christensen - 04 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=403 /] Find all technical papers here. » read more

Global IC Fabs And Facilities Report: 2024
By Liz Allan - 21 Jan, 2025 - Comments: 0

The chip industry made significant capital investments this year to build new fabs and facilities or expand existing premises. A number of sites were dedicated to SiC, GaN, DRAM, HBM, along with packaging and assembly by OSATs, and essential gases, chemicals, and other components. More than a dozen R&D centers were also established for 8-inch wafers, EUV, and advanced packaging. Investments... » read more

Chip Industry Week In Review
By The SE Staff - 17 Jan, 2025 - Comments: 0

GlobalFoundries will create a new center for advanced packaging and testing of U.S.-made essential chips within its New York manufacturing facility. A flurry of announcements on advanced semiconductors and AI rolled out this week as U.S. President Biden wrapped up his term: The Biden-Harris Administration released an Interim Final Rule on Artificial Intelligence Diffusion to strengthen ... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability
By Siemens EDA - 15 Jan, 2025 - Comments: 0

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

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