tag: low power

In-Depth Study of Low-Power MCUs For Wearables (EPFL)
By Technical Paper Link - 28 Dec, 2024 - Comments: 0

A new technical paper titled "Enabling Efficient Wearables: An Analysis of Low-Power Microcontrollers for Biomedical Applications" was published by researchers at EPFL. Abstract "Breakthroughs in ultra-low-power chip technology are transforming biomedical wearables, making it possible to monitor patients in real time with devices operating on mere {\mu}W. Although many studies have examined... » read more

Semiconductor Engineering’s Special Reports 2024
By The SE Staff - 23 Dec, 2024 - Comments: 0

Semiconductor Engineering published 36 special reports in 2024. Focus Areas Manufacturing, Packaging, Materials Test, Measurement New Fabs and Funding Memory Design Power, Performance Manufacturing, Packaging, Materials Navigating Increased Complexity In Advanced Packaging  Intel Vs. Samsung Vs. TSMC Hybrid Bonding Makes Strides Toward Manufacturability 3.5D: The Great Comp... » read more

Distributed Voltage And Frequency Scaling Gaining Traction
By Ed Sperling - 16 Dec, 2024 - Comments: 0

DVFS has been used in smart phones for more than a decade as a way of trading off power and performance when both are constrained, but much of the semiconductor industry has avoided this technique because it's too difficult to work with. That's starting to change as processing demands increase, driven by the rollout of AI everywhere and an increase in the number of features in advanced packages... » read more

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

Two Silicon Switches Driven Both Thermally and Electrically With Ultra-Low-Crosstalk (Cambridge)
By Technical Paper Link - 06 Nov, 2024 - Comments: 0

A new technical paper titled "Ultra-low-crosstalk Silicon Switches Driven Thermally and Electrically" was published by researchers at University of Cambridge and GlitterinTech Limited. Abstract "Silicon photonic switches are widely considered as a cost-effective solution for addressing the ever-growing data traffic in datacenter networks, as they offer unique advantages such as low power co... » read more

Reducing SoC Power With NoCs And Caches
By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

TFETs: Design and Operation, Including Material Selection and Simulation Methods
By Technical Paper Link - 07 Oct, 2024 - Comments: 0

A new technical paper titled "Multiscale Simulation and Machine Learning Facilitated Design of Two-Dimensional Nanomaterials-Based Tunnel Field-Effect Transistors: A Review" was published by researchers at University of Chicago and Argonne National Lab. Abstract "Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transi... » read more

Review Paper: Challenges Required To Bring the Energy Consumption Down in Microelectronics (Rice, UC Berkeley, Georgia Tech, Et al.)
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new review article titled "Roadmap on low-power electronics" by researchers at Rice University, UC Berkeley, Georgia Tech, TSMC, Intel, Harvard, et al. This roadmap to energy efficient electronics written by numerous collaborators covers materials, modeling, architectures, manufacturing, metrology and more. Find the technical paper here. September 2024. Ramamoorthy Ramesh, Sayeef Sal... » read more

KAN: Kolmogorov Arnold Networks: An Alternative To MLPs (MIT, CalTech, et al.)
By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "KAN: Kolmogorov-Arnold Networks" was published by researchers at MIT, CalTech, Northeastern University and The NSF Institute for Artificial Intelligence and Fundamental Interactions. Abstract: "Inspired by the Kolmogorov-Arnold representation theorem, we propose Kolmogorov-Arnold Networks (KANs) as promising alternatives to Multi-Layer Perceptrons (MLPs). While... » read more

Datacenter Chipmaker Achieves Double-Digit Power Reduction with Next-Gen Voltage Scaling
By proteanTecs - 11 Jun, 2024 - Comments: 0

The Customer A fabless chipmaker making 5nm networking chips for datacenters. The Challenge High power consumption due to excessive voltage guard-bands What You'll Discover: Learn how the customer safely decreased the voltage from 650 mV to an average of 608 mV, resulting in a 12.5% dynamic power reduction. This significant optimization helped the chipmaker stand out as a low-pow... » read more

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