A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill

By Mentor, a Siemens Business - 19 Oct, 2016 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Blog Review: Oct. 19

By Jesse Allen - 19 Oct, 2016 - Comments: 0

Mentor's Colin Walls provides some tips on writing portable, reusable code. Cadence's Christine Young contends that you should never use 2.5D for characterization at advanced nodes. Synopsys' Eric Huang considers one impractical use of USB heating and the IoT. Applied's Ben Lee predicts a rapid growth in China's power device manufacturing. NXP's Joppe Bos digs into the challenges of... » read more

Side-Channel Attacks Make Devices Vulnerable

By Brian Bailey - 17 Oct, 2016 - Comments: 0

As the world begins to take security more seriously, it becomes evident that a device is only as secure as its weakest component. No device can be made secure by protecting against a single kind of attack. Hypervisors add a layer of separation between tasks making sure that one task cannot steal secrets from another. Protection of the JTAG port is necessary to prevent access underneath the h... » read more

The Week In Review: IoT

By Jeff Dorsch - 14 Oct, 2016 - Comments: 0

Memory Kilopass Technology uncorked its new eNVM, which includes vertical layered thyristor DRAM technology. The key advantages, according to the company, is that it eliminates the need for DRAM refresh, can be manufactured using existing processes, and improves power and area efficiency. A full memory test chip is currently in the early stages of testing. A thyristor is basically a latch tech... » read more

The Week In Review: Design

By Jesse Allen - 14 Oct, 2016 - Comments: 0

M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

Betting On Power And Deep Learning

By Ed Sperling - 13 Oct, 2016 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, sat down with Semiconductor Engineering to talk about what investments deliver the biggest returns, how quickly, and why there are so few investors in some big growth areas. What follows are excerpts of that conversation. SE: What are you investing in these days and why? Hogan: I have about 15 active deals right now. I generally invest in thi... » read more

Deterministic ICE App Tackles ICE Limitations

By Rizwan Farooq - 13 Oct, 2016 - Comments: 0

Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out. However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. W... » read more

Seeing The Future Of Vision

By Jeff Dorsch - 13 Oct, 2016 - Comments: 0

Vision systems have evolved from cameras that enable robots to “see” on a factory floor to a safety-critical element of the heterogeneous systems guiding autonomous vehicles, as well as other applications that call for parallel processing technology to quickly recognize objects, people, and the surrounding environment. Automotive electronics and mobile devices currently dominate embedded... » read more

Getting The Power/Performance Ratio Right

By Ann Mutschler - 13 Oct, 2016 - Comments: 0

Getting to market quickly means determining as soon as possible if a concept for a new design will work or not, particularly where power and performance are concerned. Making this determination requires intimate knowledge of the scenarios in which the device will operate — and that is just the start. In order to set things up, you need to somehow model the system, which could be done in a ... » read more

Five Steps To Quality CDC Verification

By Mentor, a Siemens Business - 12 Oct, 2016 - Comments: 0

With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verifi... » read more

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tag: Mentor Graphics

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill

Blog Review: Oct. 19

Side-Channel Attacks Make Devices Vulnerable

The Week In Review: IoT

The Week In Review: Design

Betting On Power And Deep Learning

Deterministic ICE App Tackles ICE Limitations

Seeing The Future Of Vision

Getting The Power/Performance Ratio Right

Five Steps To Quality CDC Verification

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