tag: Mentor Graphics

Blog Review: Oct. 5
By Jesse Allen - 05 Oct, 2016 - Comments: 0

Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

Heterogeneous System Challenges Grow
By Ann Mutschler - 03 Oct, 2016 - Comments: 0

As more types of processors are added into SoCs—CPUs, GPUs, DSPs and accelerators, each running a different OS—there is a growing challenge to make sure these compute elements interact properly with their neighbors. Adding to the problem is this mix of processors and accelerators varies widely between different markets and applications. In mobile there are CPUs, GPUs, video and crypto pr... » read more

The Week In Review: Design
By Jesse Allen - 30 Sep, 2016 - Comments: 0

Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

EDA, IP Sales Up
By Ed Sperling - 29 Sep, 2016 - Comments: 0

EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. The only region that showed a decline was Europe, the Middle East ... » read more

Moving Automotive Test Into The Analog Domain
By Steve Pateras - 29 Sep, 2016 - Comments: 0

The amount of electronic content in passenger cars continues to grow rapidly, driven mainly by the integration of various advanced safety features. The industry’s move towards fully autonomous vehicles promises to even further increase the number of these safety features and consequentially, the electronic content required in each vehicle. Recent reports indicate that hundreds of semicondu... » read more

Building Chips That Can Learn
By Ed Sperling - 29 Sep, 2016 - Comments: 0

The idea that devices can learn optimal behavior rather than relying on more generalized hardware and software is driving a resurgence in artificial intelligence, machine leaning, and cognitive computing. But architecting, building and testing these kinds of systems will require broad changes that ultimately could impact the entire semiconductor ecosystem. Many of these changes are wel... » read more

Hypervisors: Help Or Hindrance?
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Hypervisors are seeing an increased level of adoption, but do they help or hinder the development and verification process? The answer may depend on your perspective. In the hardware world, system-level integration is rapidly becoming a roadblock in the development process. While each of the pieces may be known to work separately, as soon as they are put together, the interactions between th... » read more

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Analog Fault Simulation Challenges And Solutions
By Mentor, a Siemens Business - 28 Sep, 2016 - Comments: 0

The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types. But for analog c... » read more

Blog Review: Sept. 28
By Jesse Allen - 28 Sep, 2016 - Comments: 0

Cadence's Paul McLellan provides a glimpse of TSMC's roadmap, including what to look for at 7nm, low-power processes, and the ecosystem around the process. Mentor's Stephen Pateras notes that throughout the evolution of DFT, two rules for success have persisted. Early analysis suggests the largest DDoS attack in history, targeted at security reporter Brian Krebs, may have leveraged flaws ... » read more

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