tag: Mentor Graphics

Can You Really Fry an Egg on a CPU?
By James Forsyth - 25 Feb, 2016 - Comments: 0

Solving complex thermal models with computational fluid dynamics (CFD) requires a lot of processing power, and a central processing unit (CPU) under full load generates a fair amount of heat. But can you cook an egg on it? Search online and you can find videos of people attempting to cook on their processors—I wouldn’t recommend this as a cooling solution. However, just out of curiosity, I ... » read more

The Ultimate Shift Left
By Anupam Bakshi - 25 Feb, 2016 - Comments: 0

Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several semiconductor development teams, especially those in Fortune 500 companies, who do not have time to change their design process. They often cite various reasons such as: • Too busy with the current project. • What we have is working, so... » read more

Getting Formal About Debug
By Brian Bailey - 25 Feb, 2016 - Comments: 0

While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

Thermal Characterization of Complex Electronics
By Mentor, a Siemens Business - 24 Feb, 2016 - Comments: 0

This whitepaper describes the role of thermal transient measurement to characterize semiconductor thermal behavior. It focuses on the value measurement derived structure functions provide through interpretation of the heat flow path inside a package for use in thermal characterization, failure diagnosis, and improving simulation thermal model accuracy. Structure functions transform thermal t... » read more

Blog Review: Feb. 24
By Jesse Allen - 24 Feb, 2016 - Comments: 0

Synopsys' Graham Etchells digs through the toolbox and finds that schematic PCells can be vital in helping layout engineers tackle FinFET complexity. Cadence's Paul McLellan looks at two techniques to test the increasing number of digital gates on an automotive chip with only two pins. In the latest PCB Tech Talk Podcast, Mentor's John McMillan discusses where collaboration with MCAD fits... » read more

The Week In Review: Design/IoT
By Jesse Allen - 19 Feb, 2016 - Comments: 0

Know someone who deserves the Phil Kaufman Award for Distinguished Contributions to EDA? Nominations are open until June 30th. Tools, IP & Chips ARM debuted the Cortex-R8 processor, targeting mass storage devices and future 5G modems with a quad-core configuration and extended low-latency memory. Cadence's schematic design tool, OrCAD Capture, added the capability to export hierarc... » read more

1xnm DRAM Challenges
By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Consolidation Hits OSAT Biz
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

The outsourced semiconductor assembly and test (OSAT) industry is undergoing a new wave of acquisition activity that will dramatically reshape the packaging and test services markets. [getkc id="83" kc_name="OSATs"] have seen a considerable amount of consolidation over the years, but the industry needs a scorecard to keep track of the recent deals and the resulting fallout. One OSAT deal inv... » read more

LVS Boxing Helps Designers Knock Out Designs Quickly
By Mentor, a Siemens Business - 18 Feb, 2016 - Comments: 0

Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

When And How Should I Color My DP layout?
By David Abercrombie - 18 Feb, 2016 - Comments: 0

Designers working with advanced process technologies that require double patterning often find themselves puzzling over the best way to setup or optimize their design flows to ensure their layouts can be decomposed without time-wasting mistakes. Because manual coloring can be challenging even for experienced engineers, many prefer to use automated coloring solutions. But when is the best time a... » read more

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