What Else Is In A Node?

By Sundeep Bajikar - 21 Jun, 2018 - Comments: 0

In part one of this blog, I reported on the 2018 Industry Strategy Symposium (ISS) where Dan Hutcheson of VLSI Research led a panel with representatives of Synopsys, NVIDIA, Intel, ASML and Applied Materials. The participants discussed how the industry is focused on simultaneously squeezing more capabilities from leading-nodes, inter-nodes and trailing-nodes to drive advances in computing. I to... » read more

Chip Dis-Integration

By Brian Bailey - 14 Jun, 2018 - Comments: 2

Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging

By Brewer Science - 11 Jun, 2018 - Comments: 0

The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

What’s In A Node?

By Sundeep Bajikar - 30 May, 2018 - Comments: 0

In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

More Lithography/Mask Challenges (Part 3)

By Mark LaPedus - 16 May, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

More Nodes, New Problems

By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

New Patterning Options Emerging

By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Get Ready For Integrated Silicon Photonics

By Brian Bailey - 12 Apr, 2018 - Comments: 1

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics. "Look at the networking bandwidth used across... » read more

Executive Insight: Wally Rhines (March 2018)

By Brian Bailey - 01 Mar, 2018 - Comments: 0

Wally Rhines, president and CEO of [getentity id="22017" e_name="Mentor, a Siemens Business"], sat down with Semiconductor Engineering to discuss a wide range of industry and technology changes and how that will play out over the next few years. What follows are excerpts of that conversation. SE: What will happen in the end markets? Rhines: The end markets are perhaps more exciting from a... » read more

5 Takeaways From ISS 2018

By Mark LaPedus - 15 Feb, 2018 - Comments: 0

At the recent Industry Strategy Symposium (ISS) in Half Moon Bay, Calif., there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs and equipment. As part of the program, ISS also discussed the latest business and technology trends. In no particular order, here are my five takeaways from ISS: Ranging forecasts ... » read more

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tag: Moore’s Law

What Else Is In A Node?

Chip Dis-Integration

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging

What’s In A Node?

More Lithography/Mask Challenges (Part 3)

More Nodes, New Problems

New Patterning Options Emerging

Get Ready For Integrated Silicon Photonics

Executive Insight: Wally Rhines (March 2018)

5 Takeaways From ISS 2018

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