More Nodes, New Problems

Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.


The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes.

Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and more physics-related effects associated with three-dimensional transistor density, more functionality, and thinning dielectrics. Add to that an increased level of uncertainty about whether IP will be available at the most advanced nodes, and whether it will be adequately tested and characterized using the latest version of a foundry’s process.

“In the old days, when you would port from one technology to another, it was understood that you’d already done your design so it was no big deal,” said Deepak Sabharwal, vice president of IP engineering at eSilicon. “You scaled the schematics and re-did the layout with this new set of rules. The technology node is just a number, and it didn’t matter whether it was 40nm or 90nm. It was all the same essentially. The expectation was also that, in terms of resources and effort, if I had a design done in a previous node, I could re-use a lot of it and advance quickly to the next node.”

That worked well enough with two-dimensional structures, but it changed significantly with the rollout of finFETs.

“Devices are sitting vertically, so what’s limiting the silicon area now is metal layers,” said Sabharwal. “What the foundries have been working on is how to get to metal layers with a tighter pitch than was done in a previous node. The design rules are absolutely Draconian now. Design rule manuals are now thousands of pages, and the layout teams are pulling their hair out figuring out how to make changes without impacting another layer. It’s like a domino effect, where you make a small change in the design and it impacts 10 other things. Today, designs are put together so tightly and so finely, with absolutely tight tolerances and margins everywhere, that things become very tough.”

This also means designers and layout engineers need to work together on a daily basis, because if the layout team makes one major adjustment somewhere, it could create issues somewhere else. Still, while the problems stack up, often literally, the migration schedule is accelerating for some companies.

“The transition from 90nm to 65nm took almost four years,” observed Tom Wong, business development director in the IP group at Cadence. “From 65nm to 55nm and then to 40nm took almost three years. Even moving from 40nm planar to 28nm high-k/metal gate (HKMG) took approximately three years. Then something happened. From 28nm HKMG to 20nm took about two years. Then things start accelerating. From 20nm HKMG to 16nm finFET took less than two years. 16nm to 14nm took less than one year, and then to 10nm. We are presently at 7nm, even though 10nm wafers just started production less than one year ago.”

Compounding this acceleration, as technologies reached these fine geometries one would expect fewer foundries would be participating in this migration due to the extensive R&D and the immense CapEx costs for new fabs, he said. “The reality is very different. At least four major companies/foundries are participating in 16nm and finer geometries. Even at 7nm, there are at least three companies vying for a leading position.”

Fig. 1: Increasing complexity and design rules. Source: Mentor, a Siemens Business

Economic considerations
The economics of these moves have impacts much further upstream in the design flow. The chip industry depends on IP reuse—or more accurately IP migration from node to node—to make this economically feasible. That’s becoming difficult to sustain.

“When you move from one geometry to the next finer geometry, what happens when the nominal Vdd drops from 0.8V to 0.7V? This will change your simple IP migration project into a full-blown redesign for complex IPs such as high-speed SerDes,” Wong said. “Also, you have less design margin to play with, more complex corners for timing closure, and many more considerations to manage OCV (on-chip variation) in your simulations. This tends to drive up the cost of IP enablement and lengthen the time to deployment.”

To make matters worse, a lot of the SoC development, design enablement and IP enablement for advanced nodes is done in parallel with process learning. This means that an IP refresh may be necessary when the process finally matures or the new process is ready for mass production. So not only is the IP development process more difficult and expensive, but the whole process of developing chips becomes more costly.

“Going from 16/14nm down to 7nm, what I’m finding is we are running at 1.5X in terms of resources,” said eSilicon’s Sabharwal.

Hard vs. soft IP, nodes vs. nodelets
Hard IP migration becomes particularly difficult in this world of constant updates bound by rules.

“When we are talking about the migration of hard IP, it greatly depends first of all whether it’s a migration to a new half-node, a so called nodelet, which is considered to be an incremental change versus an original node,” said Benny Winefeld, solutions architect at Arteris IP. “Full, new-node migration was always hard, but transitioning to a half node was more doable since it was primarily an optical shrink. The DRC rules are kind of similar, the delta in various electrical characteristics is also uniform, more or less, and predictable.”

He pointed to the migration from TSMC’s 32nm to 28nm as a good example. “I won’t say it was easy, but it was totally doable. In more recent nodes, the DRC rule sets have grown much larger and more complicated, as in hundreds of rules to many thousands of rules. Plus, the delta between the base nodes and the nodelets also grew, so they’re not as similar anymore. From my recent experience, TSMC 16 and TSMC 12, which was supposed to be an incremental step, are not as similar anymore. There are quite substantial differences. If you’re trying to do an automatic translation using a smart tool that does adjustments of polygons, they need to perform much more complicated transformations. It’s not just that you can multiply by 0.8 linear scale and everything works. It’s not only that you will suddenly violate the physical rules, but the electrical characteristics may also dramatically change and will no longer work. On TSMC 12, the DRC rules are different, the libraries are different. But even so, TSMC 12nm is considered to be an incremental change.”

Moving a full node, from 16nm to 7nm is even more difficult. That requires transitioning from double patterning to a computational design platform, with completely different rules, he said.
And all of this comes to bear on the network-on-chip, which acts as the glue logic for CPUs, caches, accelerators and memories.

“Silicon allows us to do more and more on the same die, but from the design perspective you can still call it IP because SoC designers can use this NoC as a building block without the need to understand the implementation details in depth,” Winefeld said. “As long as it honors the protocols, and as long as it is logically correct and satisfies the high-level system requirements like latency, bandwidth, quality of service, it doesn’t really make sense to have this IP hardened. If you can imagine the die size, this network typically floats in the channels between the IPs that it connects, and those IPs in turn can be either hard or soft. But the NoC, for all practical purposes, is soft. The topology and layout of NoC varies greatly, and it is specific to the SoC for which it has been designed.”

Getting IP blocks to work together is only part of the problem. Being able to prove the IP in functional test chips is another.

“If you are an IP provider, then you need to get a functional test chip done on all of the lower nodes because people will ask for that,” said Ranjit Adhikary, vice president of marketing at ClioSoft. “They are not so hung up on whether it is a hard core or a soft core. They want to know whether you have the functional test chip done. With NRE costs high, that becomes a challenging situation. For small companies it becomes a tough sell to invest and put the money in the test chip without having assurances that you’re going to get a lot of orders. On the other hand, if you’re a system house, you are using your own IPs. Then, of course, it makes sense. But you still have to look at how much its going to cost and how much effort it will take, because the effort needed to migrate IP to an advanced node is quite high.”

Add to this a bunch more verification.

“These issues definitely mean a lot of extra verification, and you want to be careful about blindly waiving things without really examining the impacts of every little issue,” said John Ferguson, product marketing director at Mentor, A Siemens Business. “I suspect it also means more early test shuttles to make sure you’ve really got things dialed in. We thought and hoped that with EUV lithography that would make things better or easier and that we could start relaxing things back a little bit. It turns out it doesn’t. EUV maybe offers some relaxation on a layer or two, but not across the board. There are just too many interdependencies, and in the end it doesn’t help solve this problem. We did know it was going to be hard. There was a lot of high-level, ‘Hey, here’s a whole bunch of benefits.’ But you look in and realize you’re trading one benefit for something else. There is no free lunch.”

One possible solution to all of this, which has been gaining traction in advanced designs, involves more mixing and matching of IP and blocks developed at different process nodes.

Heterogeneity is driving new ways of thinking about SoC design, pointed out Anush Mohandass, vice president of marketing and business development at NetSpeed Systems.

“An emerging trend here is the concept of a multi-layer chip where the base layer, which may contain the I/Os and some peripheral devices actually existing in 28nm, and then all the different computes, all the things that you’re pushing performance for actually exists on a separate layer,” Mohandass said. “Perhaps that’s on 16nm or 7nm. Although it may be referred to in different ways, it needs some form of intelligence connecting it all together.”

Logically, it’s perhaps one big SoC but you partition it, he noted. “Another way to visualize it even now when there is a standard IP, people think about it as doing the divide and conquer. They say, ‘Here is my CPU subsystem. Here is my image subsystem. Here is my memory subsystem.’ You partition your design with different subsystems and you put it all together. What we’re seeing now is it’s still the same except for perhaps a couple of partitions that actually exist in a separate chip. It’s just put together in the same package. Obviously this requires a pretty sophisticated interconnect, but this multi-layer of chips is something that’s getting more and more popular with decreasing process nodes.”

Some of the problems remain the same, though, such as floor planning. And processes for some of the advanced components are taking longer to develop, even though the time between nodes is shrinking.

“Placement is showing up earlier in the flow than it was tackled previously,” said Mark Richards, technical marketing manager for physical implementation at Synopsys. “But you also have to start a design with version 0.1 or 0.5 of a process, so the overall design process takes longer. There are more interactions with lead customers to smooth everything out as the process develops. But the speed of the nodes, plus the release of nodelets in between, is making it more difficult.”

From the foundry side, it’s quicker to ramp a nodelet by shrinking the logic portion and leave everything else at the same node. Whether that makes it easier for the IP developers isn’t entirely clear yet, but this appears to be an attractive option on one level. “If you just want to use that IP exactly as is in a newer design, and some of the other stuff at the new design is going to use or take advantage of those features of the new node — that is not so bad, because normally it’s about letting you get tighter tolerances that causes you to have tougher, more difficult rules,” said Mentor’s Ferguson.

There’s another side to this, however, involving engineering resources. “There are so many process nodes that we are outstripping the supply of smart engineers in IP enablement,” said Cadence’s Wong. “Before we finish full IP enablement in one node, the next nodes emerge. I don’t know if this trend is sustainable.”

Leave a Reply