tag: Moore’s Law

Moore’s Law Debate Continues
By Ann Mutschler - 02 Nov, 2016 - Comments: 0

Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

The Battle To Embed The FPGA
By Brian Bailey - 31 Oct, 2016 - Comments: 1

There have been many attempts to embed an [gettech id="31071" comment="FPGA"] into chips in the past, but the market has failed to materialize—or the solutions have failed to inspire. An early example was [getentity id="22924" comment="Triscend"], founded in 1997 and acquired by [getentity id="22839" e_name="Xilinx"] in 2004. It integrated a CPU—which varied from an [getentity id="22186" co... » read more

GPU Accelerated Computing
By D2S - 19 Oct, 2016 - Comments: 0

The computing applications used in semiconductor design and manufacturing have ever-increasing requirements for speed, accuracy and reliability. The continuation of Moore's Law creates a perpetual demand for greater accuracy as, with each new process node, larger numbers of increasingly smaller features are crowded onto each mask and wafer. Computing farms, where thousands of central processing... » read more

Fear Of Machines
By Ed Sperling - 29 Sep, 2016 - Comments: 0

In the tech industry, the main concern over the past five decades has been about what machines could not do. Now the big worry is what they can do. From the outset of the computer age, the biggest challenges were uptime, ease of use, reliability, and as devices became more connected, the quality and reliability of that connection. As the next phase of machines begins, those problems have bee... » read more

450mm And Other Emergency Measures
By Ed Sperling - 22 Sep, 2016 - Comments: 0

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

The Zen Of Processor Design
By Ed Sperling - 15 Sep, 2016 - Comments: 0

Mark Papermaster, chief technology officer at Advanced Micro Devices, sat down with Semiconductor Engineering to discuss how to keep improving performance per watt, new packaging options, and the increasing focus on customization for specific tasks. What follows are excerpts of that conversation. SE: As we get more into the IoT and we have to deal with more data, not to mention cars where da... » read more

Focus Shifts To Architectures
By Ed Sperling - 08 Sep, 2016 - Comments: 1

Chipmakers increasingly are relying on architectural and micro-architectural changes as the best hope for improving power and performance across a spectrum of markets, process nodes and price points. While discussion about the death of [getkc id="74" comment="Moore's Law"] predates the 1-micron process node, there is no question that it is getting harder for even the largest chipmakers to st... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance
By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

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