Is The 2.5D Supply Chain Ready?

By Ed Sperling - 28 Sep, 2015 - Comments: 0

A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

Pick A Number

By Ed Sperling - 24 Sep, 2015 - Comments: 0

For the past two years there was some mumbling that 16/14nm would be short-lived, and that 10nm would be the place that foundries would invest heavily. Now the buzz is that 10nm may be skipped entirely and the next node will be 7nm. After all, 10nm is really only a half-node. Or is it? The answer depends on who's defining 10nm. The 16/14nm node is based on a 20nm back-end-of-line process, un... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge

By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

We Must Teach Chips To Feel Pain

By Imec - 17 Sep, 2015 - Comments: 0

By Guido Groeseneken When I was a doctorate student in the 1980s there was lots of wild speculation about Moore’s Law: give it another 10 years and transistors will stop getting smaller, they were saying back then. But in the end, the creativity of engineers turned out to be greater than the pessimism of the forecasters. Yet today I believe that we are close to the end of Moore’s Law.... » read more

ALD Market Heats Up

By Mark LaPedus - 17 Sep, 2015 - Comments: 1

Amid the shift to 3D NAND, finFETs and other device architectures, the atomic layer deposition (ALD) market is heating up on several fronts. Applied Materials, for example, recently moved to shakeup the landscape by rolling out a new, high-throughput ALD tool. Generally, [getkc id="250" kc_name="ALD"] is a process that deposits materials layer-by-layer at the atomic level, enabling thin and ... » read more

EUV: Cost Killer Or Savior?

By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Executive Insight: Charlie Cheng

By Ed Sperling - 14 Sep, 2015 - Comments: 1

Charlie Cheng, CEO of Kilopass, sat down with Semiconductor Engineering to talk about issues with current memory types and why the market is ready for disruptive approaches to reduce power and cost. SE: What's changing in the memory space? Cheng: Memory is a very important building block. It's a foundation and a commodity for a chip and for the system, but if you look at the big picture, ... » read more

Appetite For Services Grows

By Ed Sperling - 11 Sep, 2015 - Comments: 0

Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

Integration Or Segregation

By Brian Bailey - 10 Sep, 2015 - Comments: 0

In the Electronics Butterfly Effect story, the observation was made that the electronics industry has gone non-linear, no longer supported by incremental density and cost-reducing improvements that Moore’s Law promised with each new node. Those incremental changes, over several decades, have meant that design and architecture have followed a predictable path with very few new ideas coming in ... » read more

Challenges At Advanced Nodes

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?