tag: semiconductor design

Why Traceability Matters
By Ed Sperling - 02 Mar, 2022 - Comments: 0

More heterogeneous and increasingly dense chip designs make it much harder to stay on track with initial specifications. Paul Graykowski, senior technical marketing manager at Arteris IP, talks about matching requirements to the design, the impact of ECOs and other last-minute changes, and best practices for managing revisions. » read more

Preparing For Test Early In The Design Flow
By Ann Mutschler - 02 Mar, 2022 - Comments: 0

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage
By Synopsys - 10 Nov, 2021 - Comments: 0

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

VLSI Design Careers
By Sivakumar P R - 08 Nov, 2021 - Comments: 0

If you're planning your career in the semiconductor industry, make sure you consider processor design. Now the aspiring VLSI engineers like you can implement the open-source processor RISC-V while learning from the textbooks. But why should a VLSI engineer understand the processor design? Does everyone implement the processor as an RTL designer? In this article, I will address these question... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization
By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

Best Practices For Deploying Cliosoft SOS On AWS
By Cliosoft - 01 Sep, 2021 - Comments: 0

Semiconductor Integrated Circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and increase productivity. This eBook outlines the advantages of, and best practices, for deploying Cliosoft SOS design ... » read more

Steering The Semiconductor Industry
By Brian Bailey - 26 Aug, 2021 - Comments: 2

Progress in semiconductors has been one of the most successful engineering feats, and the industry has ridden an exponential curve longer than anything else in history. It is also a highly conservative industry that has pushed away many disruptive changes in favor of small incremental changes that minimize risk. There have been significant changes over the decades, and they often required a ... » read more

Dynamically Reconfiguring Logic
By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

Steep Spike For Chip Complexity And Unknowns
By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Next-Gen Design Challenges
By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

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