System-in-Package Challenges


Systems companies and leading-edge chipmakers are pushing past reticle limits with chiplet-based designs, often breaking compute-intensive functions into different chiplets and coupling those with other chiplets that may have been developed by different teams and at different process nodes. This is harder than it sounds, and results can vary widely even under the best circumstances. Nir Sever, ... » read more

Purpose-Built Tools for Connected Design


Modern semiconductor design is a massive, data-driven effort—often involving terabytes of files and globally distributed teams. Yet many organizations still rely on disconnected workflows and generic version control tools not designed for the scale or complexity of chip development. These fragmented systems slow innovation, reduce efficiency, and make collaboration increasingly difficult. ... » read more

Ensuring Accuracy in LLM-Generated Hardware Logic Design Automation (IBM Research)


A new technical paper "Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation" was published by researchers at IBM Research. Abstract "We show for invertible problems that transform data from a source domain (for example, Logic Condition Tables (LCTs)) to a destination domain (for example, Hardware Description Language (... » read more

EDA’s Top Execs Map Out An AI-Driven Future


Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Model-Based Systems Engineering


Today’s electronic systems are an increasingly complex combination of hardware and software components. They contain an ever-expanding range of functions, require more computing power, have to operate a wide variety of interfaces, comply with standards, and be compatible with established market solutions. Accommodating all the new functions and expanded capacity may require a larger silicon a... » read more

Optimizing Data Movement


Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Auto Sector Leads The Way In IC Security


Concerns about chip and system security are beginning to bear fruit in some markets, driven by the overlap in safety and security in automotive applications and the growing value of algorithms and complex systems in others. But how and when that security is implemented is still all over the map, and so is its effectiveness. The reasons are as nuanced as the designs themselves, which makes it... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

One Chip Vs. Many Chiplets


Experts at the Table: Semiconductor Engineering sat down to discuss the growing list of challenges at advanced nodes and in advanced packages, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Ponnusw... » read more

Globally Asynchronous, Locally Synchronous Clocks


Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

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