tag: SoC

RTL Signoff
By Ed Sperling - 03 Jun, 2013 - Comments: 0

Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

Does SoC Signoff Mean More Than RTL?
By Graham Bell - 30 May, 2013 - Comments: 0

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact grows while their causes become more obscured. This requirement is driving the shift in design exploration and handoff to the reg... » read more

FinFET Isolation: Bulk vs. SOI
By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

Shifts In Verification
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

GF’S Two Flavors Of FD-SOI
By Various Writers - 17 Apr, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.   [caption id="" align="alignleft" width="110"] Subi Kengeri, VP Advanced T... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Over 50% Of Smart Phones And Tablets Leverage SOI
By Various Writers - 18 Mar, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ In a recent press release, the SOI wafer leader Soitec said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. 50%? That’s a lot! How do they figure that? The answer: RF. [caption id="attachment_809" align="alignleft" width="549" caption="As seen here... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Smarter Things
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous. There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is... » read more

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