Goal-Driven AI

By Brian Bailey - 26 Nov, 2024 - Comments: 2

For many, the long-term dream for AI within EDA is the ability to define a set of goals and tell the computer to go design it for them. A short while later, an optimized design will pop out. All of today's EDA tools will remain hidden, if they even exist at all. You would only be limited by your imagination. But we also know that AI is not to be trusted today, especially when millions of dol... » read more

How To Speed Up LVS Verification

By Wael elManhawy - 26 Nov, 2024 - Comments: 0

Layout versus schematic (LVS) comparison is a crucial step in integrated circuit (IC) design verification, ensuring that the physical layout of the circuit matches its schematic representation. The primary goal of LVS is to verify the correctness and functionality of the design. Traditionally, LVS comparison is performed during signoff verification, where dedicated tools compare layout and sche... » read more

The Xpedition Flow

By Siemens EDA - 26 Nov, 2024 - Comments: 0

Comprehensive approach to designing electronics The complexities of modern PCB design necessitate a comprehensive approach that integrates various aspects of the entire design through manufacturing flow. The ideal design flow requires seamless cooperation and synergy across various domains, including electrical, mechanical, software, systems, test, and manufacturing. Xpedition provides a gr... » read more

RISC-V’s Software Portability Challenge

By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

Benchmark and Evaluation Framework For Characterizing LLM Performance In Formal Verification (UC Berkeley, Nvidia)

By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware" was published by researchers at UC Berkeley and NVIDIA. Abstract "The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital chip design. In particula... » read more

Pre-Silicon Verification Method Addressing Critical Aspects of Speculative Execution Vulnerability Detection

By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection" was published by researchers at Technical University of Darmstadt and Texas A&M University. "We introduce Specure, a novel pre-silicon verification method composing hardware fuzzing with Information Flow Tracking (IFT) to address speculative execution leakages. Integrating IFT enables two... » read more

RISC-V Conformance

By Brian Bailey - 31 Oct, 2024 - Comments: 0

Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is conformance, which must exist before software portability becomes possible. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO... » read more

The Growing Imperative Of Hardware Security Assurance In IP And SoC Design

By Pavani Jella - 24 Oct, 2024 - Comments: 0

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in t... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)

By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

New Challenges In IC Reliability

By Ed Sperling - 15 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.