tag: verification

Toward Agentic Verification
By Brian Bailey - 28 May, 2026 - Comments: 1

Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Why Your NoC Verification Strategy Must Consider Using Formal
By Ashish Darbari - 28 May, 2026 - Comments: 0

By Ashish Darbari and Bing Xue It’d be inconceivable these days to design a modern high-performance SoC without a network-on-chip (NoC) fabric. AI hyperscalers are inherently multi-threaded and rely on using hundreds of processing elements (PEs). Crossbar-based fabric would just not scale. What also changes with the adoption of the NoC is how to handle coherency between PEs. ACE is no long... » read more

Automating Traditional PCB Layout Verification With Electrically Based Design Rule Checks
By Rory Riggs - 28 May, 2026 - Comments: 0

Electrical verification and sign-off of a printed circuit board (PCB) is a challenging, tedious, and manual process. If time permits, this visual inspection to catch errors that might cause costly respins is done throughout the PCB layout process, but traditionally it is performed only once at the end of the design cycle. This approach creates significant project delays when issues are discover... » read more

Faster Verification Debug With AI
By Taruna Reddy - 28 May, 2026 - Comments: 0

Every stage of semiconductor development takes longer and requires more effort with each new generation of chips. At no stage is this more apparent than functional verification. Industry consensus is that verification consumes roughly two-thirds of development time and resources. Within verification, debug is the most challenging step, consuming a third to two-thirds of the effort. Any serious ... » read more

Harnessing Artificial Intelligence For Trusted IC Signoff
By Carey Robertson - 14 May, 2026 - Comments: 0

After years of behind-the-scenes work, artificial intelligence (AI) is now embedded throughout the technology world—from space exploration to everyday apps on our smartphones. There is a circular feedback loop in which we design more powerful computer chips to train AI models and use them; and then use those AI models to design even more powerful chips. The use of AI in the software used for ... » read more

ASIC Prototyping — New Design Realities Demand A New Approach
By Siemens EDA - 14 May, 2026 - Comments: 0

Modern ASIC design pushes prototypes to model vast RTL interactions across many FPGAs, often under high-bandwidth conditions that strain traditional systems. Verification teams also need fluid movement between emulation and at-speed prototyping, exposing any gaps in flow, tooling, or model continuity. This white paper presents an integrated solution that addresses these challenges through a uni... » read more

Hardware From Specifications Using AI
By Brian Bailey - 06 May, 2026 - Comments: 0

There is a lot of excitement these days surrounding the idea that AI could make it possible to go from a specification to a design with absolutely no hardware skills. Well, get in line, because this is the umpteenth potential technology that was going to make that possible. Don't get me wrong, it just might do it, but will this be an implementation that is reliable, have decent performance, ... » read more

Enabling A Critical Phase in SoC Development
By Siemens EDA - 06 May, 2026 - Comments: 0

High speed execution of an SoC model on an FPGA-based prototyping system is essential—both to permit development and verification of the full software stack and to understand hardware/software interactions—before silicon is available. But for SoC designs that include high-speed, voluminous I/O, it is equally essential that the prototype be exercised with large amounts of real-world I/O o... » read more

Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)
By Technical Paper Link - 05 May, 2026 - Comments: 0

A new technical paper, "Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL," was published by researchers at Barcelona Supercomputing Center. Abstract "The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a ho... » read more

Transforming DRC Closure At Advanced Nodes
By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

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