tag: verification

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations
By Technical Paper Link - 07 Nov, 2023 - Comments: 0

A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges
By Kunal Chhabriya - 02 Nov, 2023 - Comments: 0

In PCI Express (PCIe), a high-speed serial computer expansion bus standard, Compliance mode is used for testing the transmitter and interconnect to assess if their voltage and timing are compliant with the specification. This testing happens in the Polling Compliance state which is a dedicated state for Compliance testing in the Link Training and Status State Machine (LTSSM). In Unraveling the... » read more

A New Architecture And Verification Approach For Hardware Security Modules
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “The K2 Architecture for Trustworthy Hardware Security Modules” was published by researchers at MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) and New York University. Abstract: "K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation ... » read more

The Limits Of AI-Generated Models
By Brian Bailey - 26 Oct, 2023 - Comments: 2

In several recent stories, the subject of models has come up, and one recurrent theme is that AI may be able to help us generate models of a required abstraction. While this may be true in some cases, it is very dangerous in others. If we generalize, AI should be good for any model where the results are predominantly continuous, but discontinuities create problems. Unless those are found and... » read more

Anatomy Of A System Simulation
By Brian Bailey - 26 Oct, 2023 - Comments: 0

The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

Why Using Commercial Chiplets Is So Difficult
By Ed Sperling - 18 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts... » read more

Verifying A RISC-V Processor
By Ed Sperling - 17 Oct, 2023 - Comments: 0

Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardwa... » read more

Simplifying Power Module Verification Using Compliance Checking
By Wilfried Wessel - 05 Oct, 2023 - Comments: 0

By Wilfried Wessel, Siemens EDA; Simon Liebetegger, University of Applied Sciences, Darmstadt; and Florian Bauer, Siemens EDA Current simulation and verification methods for power modules are time-consuming. Each domain has specific solutions based on finite elements analysis, computational fluid dynamics and solvers for electric circuits like SPICE. This article investigates if it is possib... » read more

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