tag: verification

Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests
By Todd Burkholder - 27 Feb, 2025 - Comments: 0

By Todd Burkholder, Wael Abdelaziz Mahmoud, Tom Fitzpatrick, Vishal Baskar, and Mohamed Nafea The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep pace with the growing complexities, leading to longer development cycles and increased risk of design... » read more

Improving Verification Methodologies
By Brian Bailey - 27 Feb, 2025 - Comments: 0

Methodology improvements and automation are becoming pivotal for keeping pace with the growing complexity and breadth of the tasks assigned to verification teams, helping to compensate for lagging speed improvements in the tools. The problem with the tools is that many of them still run on single processor cores. Functional simulation, for example, cannot make use of an unlimited number of c... » read more

A Novel Approach For Hardware-Software Co-Verification
By Siemens EDA - 26 Feb, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

Pre-Silicon Verification Of Die-to-Die IP With Novel ESD Protection
By Synopsys - 26 Feb, 2025 - Comments: 0

All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate. Die-to-die interface IP includes extremely large numbers of I/Os, trending towards... » read more

Beyond Simulation: Transforming Early IC Design With Insight Analyzer
By Siemens EDA - 13 Feb, 2025 - Comments: 0

Traditional verification methods are proving inadequate for addressing critical reliability challenges in today's increasingly complex integrated circuit (IC) designs. Modern IC design requires a proactive approach to verification that emphasizes early-stage analysis. The shift-left methodology enables earlier identification of potential design risks, addressing the complex challenges of IP blo... » read more

Enhancing Reliability For Automotive ICs
By Matthew Hogan - 06 Feb, 2025 - Comments: 0

As an IC designer focused on automotive applications, reliability is likely one of your top priorities. The components you develop need to withstand extreme environmental conditions, maintain performance over extended lifetimes, and meet rigorous industry standards. Failure is simply not an option when it comes to automotive electronics. Achieving the required levels of reliability can be a ... » read more

Beyond Simulation: Transforming Early IC Design With Insight Analyzer
By Siemens EDA - 06 Feb, 2025 - Comments: 0

Traditional verification methods are proving inadequate for addressing critical reliability challenges in today's increasingly complex integrated circuit (IC) designs. Modern IC design requires a proactive approach to verification that emphasizes early-stage analysis. The shift-left methodology enables earlier identification of potential design risks, addressing the complex challenges of IP blo... » read more

What’s Missing From Predictions
By Brian Bailey - 30 Jan, 2025 - Comments: 1

At this point everyone has made their predictions for the year, but there is one thing many people get wrong. Predictions are not about innovation. They are about pain and what is causing it. This industry is risk-averse, and everyone wants to continue doing what they are doing. But there comes a point when it's so painful to continue that something has to change. Having something that is... » read more

Complete Transistor Level Electrical Checks With Formal Analysis
By Almitra Pradhan - 30 Jan, 2025 - Comments: 0

Nothing is worse for a design team than a chip that fails to work in the bringup lab. Electrical problems are historically a major cause of such failures. Power leaks, power-ground DC paths, missing level shifters, and design flaws such as high fanout lead to unexpected power consumption, incorrect functionality, and even total meltdown. Designers learned years ago that pre-silicon electrical c... » read more

EDA Revenue Hit Record High In Q3
By Ed Sperling - 14 Jan, 2025 - Comments: 0

EDA and IP revenue increased 8.8% in Q3 2024, dragged down from the double-digit growth of recent quarters by a softening in sales to China, according to the most recent report by SEMI. For more than a decade, China's growth propped up the entire tools industry, reporting consistent double-digit growth growth that reached as high as 40% quarter over quarter. But with ongoing trade restrictio... » read more

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