Maximizing Coverage Metrics with Formal Unreachability Analysis

By Synopsys - 25 Sep, 2024 - Comments: 0

Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

Simulation Replay Tackles Key Verification Challenges

By Robert Ruiz - 12 Sep, 2024 - Comments: 0

Simulation lies at the heart of both verification and pre-silicon validation for every semiconductor development project. Finding functional or power problems in the bringup lab is much too late, leading to very expensive chip turns. Thorough simulation before tapeout, coupled with comprehensive coverage metrics, is the only way to avoid surprises in silicon. However, the enormous size and comp... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)

By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

Managing Complexity And A Left Shift: Reconfigurable Mixed-Signal Circuits For Complex Integrated Systems

By Bjorn Zeugmann - 08 Aug, 2024 - Comments: 0

By Björn Zeugmann and Benjamin Prautsch The chip market is growing worldwide; it’s projected to nearly double by 2030 to over one trillion dollars. Most of this market is made up of digital functions in the form of logic, microprocessors, and memory. Although analog ICs account for only around 15% of the total, they are key components for overall systems and are therefore almost always pr... » read more

Formal Verification of Security Properties On RTL Designs

By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “RTL Verification for Secure Speculation Using Contract Shadow Logic” was published by researchers at Princeton University, MIT CSAIL, and EPFL. Abstract: "Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from unknown vulnerabilities. Thus... » read more

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity

By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies

By Geeta Arora - 18 Jul, 2024 - Comments: 0

Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)

By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

Holistic Verification and Validation of Automotive IP for Functional Safety SoCs

By Synopsys - 03 Jul, 2024 - Comments: 0

Automotive functional safety systems have strict requirements to help avoid damages to life and property in case of a failure. As technology becomes more complex, there are increasing safety-related risks from systematic failures and random hardware failures that must be considered during product development. Standards like ISO 26262 provide guidance to mitigate such safety-related risks, by de... » read more

Verification Tools Straining To Keep Up

By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

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