tag: verification

A Reliability Baseline Is Essential For Today’s Complex IC Designs
By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Debugging Debug
By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Inside UVM, Take Two
By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

AI And Machine Learning Drive New SoC Verification Choices
By Frank Schirrmeister - 22 Feb, 2018 - Comments: 0

I have previously written about the choices that design teams have when choosing specific verification engines—virtual, formal, simulation, emulation, FPGA and actual silicon. As a new class of SoC is emerging for machine learning and artificial intelligence with complexities previously unheard of, they further deepen the challenge of choosing the right tool for the job. Even the choice betwe... » read more

The Value Of Trust
By John Ronco - 12 Feb, 2018 - Comments: 0

It took 40 years for Alexander Graham Bell’s telephone to go from 10% to 40% global saturation. The smartphone repeated that market penetration in less than a tenth of the time. But even the success of the smartphone is being eclipsed by the lightning pace at which Internet of Things (IoT) products are being born, with Gartner predicting that 95% of all technology products will be IoT-capable... » read more

Bridging Machine Learning’s Divide
By Brian Bailey - 08 Feb, 2018 - Comments: 0

There is a growing divide between those researching [getkc id="305" comment="machine learning"] (ML) in the cloud and those trying to perform inferencing using limited resources and power budgets. Researchers are using the most cost-effective hardware available to them, which happens to be GPUs filled with floating point arithmetic units. But this is an untenable solution for embedded infere... » read more

How Robust Is Your ESD Protection? Are You Sure?
By Derong Yan - 08 Feb, 2018 - Comments: 0

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

DVCon Committee Picks
By Brian Bailey - 25 Jan, 2018 - Comments: 0

A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting loaded with added complexity from heterogeneous multi-core systems, functional safety, neural networks and security-in addition to increasing size. Companies that do not keep up with the lates... » read more

Raising SoC Development Productivity With Portable Stimulus
By Mark Olen - 25 Jan, 2018 - Comments: 0

The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable verification IP. A remaining bottleneck in the SoC development process stems from the inability to re... » read more

Predictions: Methodologies And Tools
By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

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