tag: verification

Choosing The Right Superlinting Technology For Early RTL Code Signoff
By Cadence - 28 Jun, 2017 - Comments: 0

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for successful implementation. Traditional lint tools have become ineffective in evaluating RTL code for today’s larger, more complex designs. However, superlinting technology, such as the Cadence J... » read more

Verification And The IoT
By Ed Sperling - 28 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Wednesday At DAC
By Brian Bailey - 22 Jun, 2017 - Comments: 0

Wednesday at DAC started off in usual fashion with a keynote. For the third day, the focus of the talk was the IoT and how significant the change is going to be. Tyson Tuttle, CEO of Silicon Labs, was the speaker. While there are a lot of figures about how many devices will be connected in the future, Tuttle put it into a different perspective. "There will 70B connected devices by 2025 worth $... » read more

Tuesday At DAC
By Brian Bailey - 21 Jun, 2017 - Comments: 0

Accellera got everyone out of bed early this morning to talk about the just announced early access release of Portable Stimulus. The panel was made up with people from user companies. Semiconductor Engineering will be providing full coverage of this event, but perhaps the important message is that the panelists were eager to get adoption within their companies but knew that there would be chall... » read more

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation
By Progyna Khondkar - 08 Jun, 2017 - Comments: 0

INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

Verification And The IoT
By Ed Sperling - 31 May, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Verification Cowboys
By Brian Bailey - 29 May, 2017 - Comments: 0

There was an event at DVCon that was both fun and serious. It was a panel of verification startup executives with the title "Ride with the Verify Seven." Many of you know [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"] who were the sponsors of the event, along with [getentity id="22914" e_name="ESD Alliance"], the organizat... » read more

Verification And Validation Don’t Mean The Same Thing
By Tom De Schutter - 25 May, 2017 - Comments: 0

While often used intermixed, verification and validation are quite different procedures with different goals and different means to achieve those goals. No better way to clear up the confusion by starting with some definitions as stated by Wikipedia, https://en.wikipedia.org/wiki/Verification_and_validation: “Verification is intended to check that a product, service, or system (or porti... » read more

Formal Verification’s Continental Divide
By Dave Kelf - 25 May, 2017 - Comments: 0

Formal verification is picking up steam with engineering groups worldwide doing complex functional verification for bug-free and reliable digital chips. In fact, many difficult verification challenges are solved with formal verification, given its flexibility in targeting a broad range of verification challenges. Recent advances in formal verification’s ease of use and capacity has made it an... » read more

Respecting Reset
By Brian Bailey - 25 May, 2017 - Comments: 0

Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

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