Tuesday At DAC


Accellera got everyone out of bed early this morning to talk about the just announced early access release of Portable Stimulus. The panel was made up with people from user companies. Semiconductor Engineering will be providing full coverage of this event, but perhaps the important message is that the panelists were eager to get adoption within their companies but knew that there would be chall... » read more

The Week In Review: Design


M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Chip Test Shifts Left


“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

Verification Unification


There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Moore’s Law: Toward SW-Defined Hardware


Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

Design Complexity Drives New Automation


As design complexity grows, so does the need for every piece in the design flow—hardware, software, IP, as well as the ecosystem — to be tied together more closely. At one level, design flow capacity is simply getting bigger to accommodate massive [getkc id="185" kc_name="finFET"]-class designs. But beyond sheer size, there are new interactions in the design flow that place much more emp... » read more

The Week In Review: Design


M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

The Week In Review: Design


M&A Siemens closed the acquisition of Mentor Graphics, making Mentor now part of Siemens' product lifecycle management (PLM) software business. The $4.5 billion deal, announced last November, brings Siemens into the IC design tool and embedded software markets and expands Siemens' multi-physics and electronic simulation capabilities in the growing digital twin space, which ties together ... » read more

Blog Review: March 29


In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

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