tag: Accellera

Blog Review: Sept. 30
By Jesse Allen - 30 Sep, 2015 - Comments: 0

In an increasingly networked world, NXP's Lars Reger advocates for a change of perspective: one which places data protection and the security of end customers and users at the heart. Differential power analysis has been on the mind of Rambus' Aharon Etengoff recently as increasing numbers of SIM cards are being cracked, plus some counter measures that can be used. Even wondered about the ... » read more

ESL: 20 Years Old, 10 To Go
By Brian Bailey - 23 Sep, 2015 - Comments: 2

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Blog Review: Sept. 9
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

The Week In Review: Design/IoT
By Jesse Allen - 28 Aug, 2015 - Comments: 0

M&A Tessera boosted its 2.5D and 3D-IC capabilities with the acquisition of Ziptronix. The $39 million cash purchase adds a low-temperature wafer bonding technology platform, which has been licensed to Sony for volume production of CMOS image sensors. Numbers Semico Research forecasts that the SoC market will approach $200 billion by 2019. According to its analysis, average die are... » read more

The Week In Review: Design/IoT
By Jesse Allen - 21 Aug, 2015 - Comments: 0

Chips Rambus moved into the fabless market with the announcement that it is developing memory controller chips, expanding the company's business beyond just creating IP for the memory and security markets. Read Ed Sperling's full analysis. Standards Accellera updated the Standard Co-Emulation Modeling Interface (SCE-MI). The newest version of the standard, SCE-MI 2.3, expands the set o... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

The Week In Review: Design/IoT
By Jesse Allen - 31 Jul, 2015 - Comments: 0

M&A ARM acquired Israel-based Sansa Security, a provider of hardware security IP and software for advanced system-on-chip components deployed in IoT and mobile devices. The company's technology is currently deployed across a range of smart connected devices and enterprise systems. Sansa IP will be integrated into ARM's TrustZone and IoT portfolios. Standards Accellera sent UVM 1.2 ... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Wrong Verification Revolution Offered
By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

DAC 2015: Day 3
By Brian Bailey - 10 Jun, 2015 - Comments: 0

The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled "Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+." The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yan... » read more

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