tag: Achronix

FPGA Design Tradeoffs Getting Tougher
By Ann Mutschler - 16 Sep, 2019 - Comments: 0

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some ... » read more

How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
By Achronix - 09 Sep, 2019 - Comments: 0

Intelligent server adapters, or SmartNICs, boost server performance in cloud and private data centers by offloading network processing workloads and tasks from server CPUs. Offloading network processing to a SmartNIC is not a new concept — for example, there are NICs that offload some network-processing functions such as checksum computation and segmentation. However, the rapid explosion in d... » read more

IP Security In FPGAs
By Ed Sperling - 05 Sep, 2019 - Comments: 0

Quinn Jacobson, strategic architect at Achronix, talks about security in FPGAs, including how to prevent reverse engineering of IP, how to make sure the design is authentic, and how to limit access to IP in transit and in the chip. » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Chiplets, Faster Interconnects, More Efficiency
By Ed Sperling - 22 Aug, 2019 - Comments: 1

Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Smart NiCs
By Ed Sperling - 05 Aug, 2019 - Comments: 1

Manish Sinha, strategic planning for marketing and business at Achronix, talks with Semiconductor Engineering about what’s changing in networking interface cards, how to get more performance out of these devices, and how much needs to be in hardware versus software. » read more

Solving 5G’s Thorniest Issues
By Ed Sperling - 01 Aug, 2019 - Comments: 0

5G rollouts are beginning to hit the market, accompanied by a long list of unsolved technical and business issues surrounding this next-generation wireless technology. But progress is being made on some of the key challenges facing this technology, even though not all of those solutions will be in place at launch. The real challenges are with millimeter-wave implementations of 5G, which oper... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Partitioning Drives Architectural Considerations
By Ann Mutschler - 19 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

How To Improve ML Power/Performance
By Ed Sperling - 12 Jul, 2019 - Comments: 0

Raymond Nijssen, vice president and chief technologist at Achronix, talks about the shift from brute-force performance to more power efficiency in machine learning processing, the new focus on enough memory bandwidth to keep MAC functions busy, and how dynamic range, precision and locality can be modified to improve speed and reduce power. » read more

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