tag: advanced packaging

Complex Heterogeneous Integration Drives Innovation In Semiconductor Test
By Jeorge Hurtarte - 15 Oct, 2024 - Comments: 0

Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The automated test equipment (ATE) industry is responding, developing and utilizing more sophisticated test equipment capable of handling the diverse functionalities and interfaces needed to test heterogeneous... » read more

Securing Advanced Packaging Supply Chain With Inherent HW Identifiers Using Imaging Techniques
By Technical Paper Link - 14 Oct, 2024 - Comments: 0

A new technical paper titled "Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging" was published by researchers at University of Florida and University of Cincinnati. "This work visits the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches, and proposes the notion of inherent... » read more

UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall
By Ramin Farjadrad - 14 Oct, 2024 - Comments: 0

With the Open Compute Project (OCP) Summit upon us, it’s an appropriate time to talk about chiplet interconnect (in fact the 2024 OCP Summit has a whole day dedicated to the multi-die topic, on October 17). Of particular interest is the Bunch of Wires (BoW) interconnect specification that continues to evolve. At OCP there will be an update and working group looking at version 2.1 of BoW. (... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Barriers To Chiplet Sockets
By Brian Bailey - 30 Sep, 2024 - Comments: 0

Experts At The Table: Demand for chiplets is growing, but debate continues about whether standards and general-purpose chiplets will kick-start the commercialization boom, or whether success will come through customization of those chiplets. Semiconductor Engineeering sat down to discuss these and other related issues with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technol... » read more

Emerging Technologies Driving Heterogeneous Integration
By Ed Sperling - 24 Sep, 2024 - Comments: 0

As chips are disaggregated into chiplets, more features are being added into these devices that chipmakers were unable to include in the past due to reticle size limits and the high cost of scaling everything to the latest process node. This has opened the door to new architectures, new materials such as glass substrates, and a variety of new challenges. Dick Otte, president and CEO of Promex I... » read more

How Die Dimensions Challenge Assembly Processes
By Anne Meixner - 19 Sep, 2024 - Comments: 1

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To fully enable a multi-chiplet ecosystem, standardized component handling and interfaces are needed. The underlying concept is similar to LEGO blocks that simply snap together, yet it's nowhere near t... » read more

SIA’s Report On the State of the U.S. Semiconductor Industry
By Technical Paper Link - 18 Sep, 2024 - Comments: 0

The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report this week, highlighting opportunities for growth, current and emerging challenges, and relevant metrics.  The report reviews the progress made on implementation of the CHIPS Act and associated manufacturing incentives. Supply chain rebalancing, workforce challenges, geopolitics and globa... » read more

What Comes After HBM For Chiplets
By Brian Bailey - 18 Sep, 2024 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss what will trigger the creation of a commercial chiplet marketplace, and what those chiplet-based designs will look like, with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technology at Marvell; Kevin Yee, senior director of IP and ecosystem marketing at Samsung; Sailesh Kumar, CEO of Baya Systems; and Tanuja... » read more

Defect Challenges Grow At The Wafer Edge
By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

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