Chiplets Add New Power Issues


Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

New Innovative Way To Functionally Verify Heterogeneous 2D/3D Package Connectivity


Historically, IC package design has been a relatively simple task which allowed the die bumps to be fanned out to a geometry suitable for connecting to a printed circuit board. The package netlist was often captured by the package designer, typically using Excel to manually assign net names to the desired die bumps and BGA balls to achieve the intended connection. Modern package and interpos... » read more

Challenges Grow For Medical ICs


Demand for medical ICs used inside and outside the body is growing rapidly, but unique manufacturing and functional requirements coupled with low volumes have turned this into a complex and extremely challenging market. Few semiconductor applications demand this level of precision, reliability, and long-term stability. Unlike consumer electronics, where failure might mean a reboot or chip re... » read more

Lines Blurring Between Supercomputing And HPC


Supercomputers and high-performance computers are becoming increasingly difficult to differentiate due to the proliferation of AI, which is driving huge performance increases in commercial and scientific applications and raising similar challenges for both. While the goals of supercomputing and high-performance computing (HPC) have always been similar — blazing fast processing — the mark... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

Back-End Packaging And Test: From Lessons Learned To Future Innovations


The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging an... » read more

Advanced Packaging Evolution: Chiplet And Silicon Photonics-CPO


As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as a crucial solution for alleviating bandwidth bottlenecks. Tod... » read more

Developing Systems For Heterogeneous Integration: Insights From HiCONNECTS


The European semiconductor ecosystem continues to evolve, driven by the ambitions outlined in the EU Chips Act. With goals to strengthen Europe’s technological leadership and double its semiconductor manufacturing market share to 20% by 2030, collaboration across the value chain is imperative. Heterogeneous Integration for Connectivity and Sustainability (HiCONNECTS), a Horizon Europe-funde... » read more

What’s Next In Advanced Packaging?


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC progress and issues, photonics, and tradeoffs with different interposers and bridge technologies, with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What fo... » read more

FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling


A new technical paper titled "Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies" was published by researchers at Arizona State University. Abstract "Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through i... » read more

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