tag: advanced packaging

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

New Issues In Power Semiconductors
By Ed Sperling - 26 Feb, 2024 - Comments: 0

The number of challenges is growing in power semiconductors, just as it is in traditional chips. Thermal dissipation and gradients, new design rules, and layout issues need to be considered, especially in the context of higher voltage and increased performance demands. Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about issues in int... » read more

Intel, And Others, Inside
By Ed Sperling - 22 Feb, 2024 - Comments: 2

Intel this week made a strong case for how it will regain global process technology leadership, unfurling an aggressive technology and business roadmap that includes everything from several more process node shrinks that ultimately could scale into the single-digit angstrom range to a broad shift in how it approaches the market. Both will be essential for processing the huge amount of data for ... » read more

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 0

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Re-architecting Hardware For Energy
By Brian Bailey - 15 Feb, 2024 - Comments: 0

A lot of effort has gone into the power optimization of a system based on the RTL created, but that represents a small fraction of the possible power and energy that could be saved. The industry's desire to move to denser systems is being constrained by heat, so there is an increasing focus on re-architecting systems to reduce the energy consumed per useful function performed. Making signifi... » read more

IC Package Physical Design Best Practices
By Siemens EDA - 15 Feb, 2024 - Comments: 0

Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits... » read more

Heterogeneous Integration And Electronics Packaging Manufacturing Roadmap (SEMI & UCLA)
By Technical Paper Link - 09 Feb, 2024 - Comments: 0

A report titled “Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP)” was published by researchers at SEMI and the University of California Los Angeles (UCLA)'s Center for Heterogeneous Integration and Performance Scaling (CHIPS), and funded by the National Institute of Standards and Technology (NIST). MRHIEP Goals: "The goal of MRHIEP is to develop an o... » read more

Inspection, Metrology Issues In Advanced Packages
By Gregory Haley - 08 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to inspect and measure smaller features across large areas in advanced packaging, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at O... » read more

Yield Tracking In RDL
By Ed Sperling - 07 Feb, 2024 - Comments: 0

Yield is a much bigger issue when it comes to panel-level packages, which may contain up to 24 RDL layers. Just finding the defects is a massive challenge, let alone understanding how they will impact the entire device. Many of these advanced packages are being used in data centers for generative AI, and killer defects caused by bridges and opens can cause serious problems. What happens, for in... » read more

Why There Are Still No Commercial 3D-ICs
By Brian Bailey - 29 Jan, 2024 - Comments: 0

Building chips in three dimensions is drawing increased attention and investment, but so far there have been no announcements about commercial 3D-IC chips. There are some fundamental problems that must be overcome and new tools that need to be developed. In contrast, the semiconductor industry is becoming fairly comfortable with 2.5D integration, where individual dies are assembled on some k... » read more

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