Low Temperature Cu-Cu Bonding for Advanced Packaging (NYCU)


A new technical paper titled "Thermal stability enhancement of low temperature Cu-Cu bonding using metal passivation technology for advanced electronic packaging" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work investigates the thermal stability of Cu-Cu bonding using a thin Ag passivation layer in applications targeting advanced packaging. Co... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies


Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

A Clear Advantage: Precision Glass Carrier Inspection For AI And HPC Markets


If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers. These carriers are becoming essential ... » read more

Surface Metrology for Hybrid Bonding in Advanced Semiconductor Packaging


Achieving a reliable hybrid bond requires both surfaces to be pristine. To support this requirement, metrology methods such as atomic force microscopy (AFM) and atomic force profilometry (AFP) are critical for surface characterization and process optimization. AFM delivers localized, high-resolution surface measurements, while AFP provides complementary large-area topography scans that ... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Reliability And Traceability In Advanced Packages


The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications


The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

When To Move To Multi-Die Assemblies


As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Structural Integrity Assessment of IC Packaging Using Scanning Acoustic Microscopy (Arizona State Univ., Fraunhofer IMWS)


A new technical paper titled "Recent Progress in Structural Integrity Evaluation of Microelectronic Packaging Using Scanning Acoustic Microscopy (SAM): A Review" was published by researchers at Arizona State University and Fraunhofer Institute for Microstructure of Materials and Systems IMWS. Abstract "Microelectronic packaging is crucial for protecting, powering, and interconnecting semi... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips


The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

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