tag: advanced packaging

Reliability Risks Shift To The Materials Stack
By Gregory Haley - 18 Dec, 2025 - Comments: 0

The semiconductor industry’s push into 3D integration and large-format substrates has fundamentally changed the role of materials in packaging. What were once structural supports and electrical insulators have become critical performance limiters. Modern packages contain far more polymers, adhesives, advanced dielectrics, thermal materials, and composite laminates than previous generations... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities
By Cassandra Melvin - 18 Dec, 2025 - Comments: 0

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Advanced Packaging: IPL Reflow Technology For Thermal Regulation (Sungkyunkwan Univ.)
By Technical Paper Link - 05 Dec, 2025 - Comments: 0

A new technical paper titled "A color-coded light-induced heating technology for Pb-free solder joints of advanced multi-semiconductor packaging" was published by researchers at Sungkyunkwan University. Excerpt from paper: "This study introduces a color-coded intense pulsed light (IPL) reflow process, leveraging differential light absorption for localized thermal modulation, enabling simu... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

Simplifying ESD Protection and Inter-Chiplet Signaling In Future 2.5D/3D Packaging Technologies (Arizona State, Univ. of Minnesota)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity" was published by researchers at Arizona State University and University of Minnesota. Abstract: "The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

Leveraging NEMS To Address Critical Hardware Security Challenges In Advanced Packaging (U. of Florida)
By Technical Paper Link - 24 Nov, 2025 - Comments: 0

A new technical paper titled "Nanoelectromechanical Systems (NEMS) for Hardware Security in Advanced Packaging" was published by researchers at University of Florida. Abstract "As hardware security threats escalate across semiconductor manufacturing and advanced packaging, there is a growing need for novel physical mechanisms to counter sophisticated attacks such as tampering, counterfeit... » read more

Advanced Packaging Traceability And Root Cause Analysis
By Aftkhar Aslam - 20 Nov, 2025 - Comments: 0

The semiconductor industry is undergoing a profound transformation. What once centered on single-die silicon packaged in QFN or BGA formats has evolved into a landscape of multi-die integration, chiplets, 3D stacking, and photonics coupling. These advanced packaging architectures are redefining design, manufacturing, and test paradigms—enabling new levels of performance, efficiency, and funct... » read more

The Thermal Trap: How Dielectrics Limit Device Performance
By Gregory Haley - 20 Nov, 2025 - Comments: 1

The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

Navigating Geopolitical Shifts And AI-Driven Growth: Insights From The SEMICON West 2025 Market Symposium
By Clark Tseng - 20 Nov, 2025 - Comments: 0

By Clark Tseng and Nishita Rao The 2025 SEMICON West Market Symposium brought together leading analysts and strategists to decode the powerful forces shaping the global semiconductor market. Building on last year’s focus on fabless growth and workforce initiatives, this year’s sessions centered on the rising influence of geopolitics, trade policy, and AI-driven investment. Experts from... » read more

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