tag: advanced packaging

Rethinking Design, Workflow For 3D
By Karen Heyman - 26 Oct, 2023 - Comments: 0

In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Gearing Up For Hybrid Bonding
By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Streamlining Failure Analysis Of Chips
By Anne Meixner - 10 Oct, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss how increasing complexity in semiconductor and packaging technology is driving shifts in failure analysis methods, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hak... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Building Better Bridges In Advanced Packaging
By Laura Peters - 21 Sep, 2023 - Comments: 1

The increasing challenges and rising cost of logic scaling, along with demands for an increasing number of features, are pushing more companies into advanced packaging. And while that opens up a slew of new options, it also is causing widespread confusion over what works best for different processes and technologies. At its core, advanced packaging depends on reliable interconnects, well-def... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging
By Amkor - 21 Sep, 2023 - Comments: 0

Bridge technology is a promising heterogeneous integration (HI) solution for application-specific integrated circuits (ASICs) and high bandwidth memory (HBM). The bridge dies provide localized communications among the multiple system on chips (SoCs) in a single package. In Amkor's bridge technology, S-Connect provides die-to-die connections with fine pitch [1]. Prototype S-Connect technology wa... » read more

Challenges Of Testing Advanced Packages
By Ed Sperling - 19 Sep, 2023 - Comments: 0

The number of things that can wrong in assembly and test increases as more chips are added into a package. Testing is the usual guarantor of a reliable device, but in an advanced package there are all sorts of new issues — more contacts, different handling requirements, the necessary thermal conditions for test, and variation within the package. George Harris, vice president of global test se... » read more

Sweeping Changes For Leading-Edge Chip Architectures
By Ed Sperling - 08 Sep, 2023 - Comments: 0

Chipmakers are utilizing both evolutionary and revolutionary technologies to achieve orders of magnitude improvements in performance at the same or lower power, signaling a fundamental shift from manufacturing-driven designs to those driven by semiconductor architects. In the past, most chips contained one or two leading-edge technologies, mostly to keep pace with the expected improvements i... » read more

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

Preparing For Commercial Chiplets
By Ed Sperling - 24 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of tha... » read more

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