tag: advanced packaging

Interconnect Innovations In High Bandwidth Memory: Part 2
By Damon Tsai - 14 Oct, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman Interconnect technology in high bandwidth memory (HBM) is at a fork in the road. One direction leads to tried-and-true microbump technology, and the other leads to a compelling alternative, hybrid bonding. Both technologies are evolving to address the stringent requirements of next generation HBM in pursuit of increased I/O density supporting high... » read more

Enabling In-Line Process Control for Hybrid Bonding Applications
By Onto Innovation - 14 Oct, 2025 - Comments: 0

As demand grows for high-performance computing (HPC) and AI-driven applications, manufacturers are turning to hybrid bonding to enable the ultra-dense 3D integration required for next-generation chip architectures. This advanced packaging technology presents significant process challenges. Surface preparation must be precisely controlled to eliminate particles, excess recess, and copper pad ... » read more

How 3D-IC Will Change Chip Design
By Ed Sperling - 08 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

CDI For The Metrology Of Copper Pads Used In Hybrid Bonding (Paul Scherrer Institute, Samsung)
By Technical Paper Link - 03 Oct, 2025 - Comments: 0

A new technical paper titled "Coherent diffractive imaging simulations for wafer inspection of periodic structures" was published by researchers at the Paul Scherrer Institute and Samsung. Excerpt "We present a study of phase retrieval algorithms applied to the metrology of copper pad topography for hybrid bonding. We demonstrate that by including a priori information in the update functi... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control
By Gregory Haley - 02 Oct, 2025 - Comments: 0

When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging
By Gregory Haley - 18 Sep, 2025 - Comments: 0

In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Interconnect Innovations In High Bandwidth Memory: Part 1
By Damon Tsai - 09 Sep, 2025 - Comments: 0

By Damon Tsai, Woo Young Han, and Tim Kryman The demand for high bandwidth memory (HBM) is accelerating across the semiconductor industry, driven by boundary-pushing artificial intelligence, high-performance computing, and advanced graphics. These technologies require access to vast datasets, which in turn increases the need for memory solutions that combine speed, density, and power efficie... » read more

Navigating Reliability Potholes: Early 3D Stress Analysis For Automotive ICs
By Shetha Nolke - 04 Sep, 2025 - Comments: 0

The rise of 3D integrated circuits (ICs) and heterogeneous packaging is reshaping how automotive ICs fulfill demanding analog and sensor requirements. Whether for radar, lidar, sensor fusion or domain controllers, advanced packaging enables new levels of integration—and performance—in automotive electronics. Yet, as these architectures grow more complex, they also introduce new forms of mec... » read more

Chiplet Design Considerations
By Robert Kruger - 28 Aug, 2025 - Comments: 0

Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs
By Bryon Moyer - 21 Aug, 2025 - Comments: 0

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

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