tag: advanced packaging

Transferable Hybrid Bonding Technique That Allows For High Integration Density In Advanced Packaging
By Brewer Science - 21 Aug, 2025 - Comments: 0

A technical paper titled "Hierarchical Multi-Layer and Stacking Vias with Novel Structure by Transferrable Cu/Polymer Hybrid Bonding for High Speed Digital Applications" was published by researchers at Industrial Technology Research Institute (ITRI) and Brewer Science. The paper demonstrates a "novel structure with hierarchical multi-layer stacking vias as well as transferred hybrid bonding,... » read more

Advanced Electrical Test Capability For Better Defect Signature Detection In Advanced Package Development
By Jesse Ko - 12 Aug, 2025 - Comments: 0

As the semiconductor world excitingly explores the potential of new advanced package solutions for their intricate and novel designs, challenges arise from undetected defects caused by the complexity of the designs and the lack of accessibility to the interconnects for testing. This typically results in a long cycle time to achieve yield entitlement. Undetected defects at the development stage ... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
By Gregory Haley - 12 Aug, 2025 - Comments: 1

As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

Issues In Ramping Advanced Packaging
By Ed Sperling - 05 Aug, 2025 - Comments: 0

Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entir... » read more

Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)
By Technical Paper Link - 30 Jul, 2025 - Comments: 0

A new technical paper titled "Hybrid Bonding with Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography" was published by researchers at Seoul National University of Science and Technology. Abstract "Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among thes... » read more

On-Die And In-Package Interconnects: eBook
By Bryon Moyer - 28 Jul, 2025 - Comments: 0

We live in the Information Age, but if information cannot get to where it's intended to go, it does no good. And the way information gets from here to there is through interconnects. This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re constructed. As always, we consider the design, test, reliability, and security impli... » read more

Using Picosecond Ultrasonic Technology For AI Packages: Part 2
By Cheolkyu Kim - 10 Jul, 2025 - Comments: 0

Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges invol... » read more

How Advanced Packaging Is Reshaping Inspection
By Gregory Haley - 10 Jul, 2025 - Comments: 0

As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

3D-IC Stress Analysis
By Shetha Nolke - 08 Jul, 2025 - Comments: 0

The semiconductor industry is undergoing a transformation as 3D integrated circuits (ICs) and heterogeneous packaging become mainstream. With these advances comes the promise of higher functional density, a smaller footprint and enhanced system performance. However, these same innovations introduce new mechanical stressors within complex assemblies, posing novel reliability risks across the dev... » read more

Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution" was published by researchers at Intel Corporation. Abstract "The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigat... » read more

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