Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Precise Control Needed For Copper Plating And CMP

By Anne Meixner - 20 Jun, 2024 - Comments: 0

Chipmakers are relying on machine learning for electroplating and wafer cleaning at leading-edge process nodes, augmenting traditional fault detection/classification and statistical process control in order to extend the usefulness of copper interconnects. Copper is well understood and easy to work with, but it is running out of steam. At 5nm and below, copper plating tools are struggling to... » read more

Predicting And Preventing Process Drift

By Gregory Haley - 22 Apr, 2024 - Comments: 0

Increasingly tight tolerances and rigorous demands for quality are forcing chipmakers and equipment manufacturers to ferret out minor process variances, which can create significant anomalies in device behavior and render a device non-functional. In the past, many of these variances were ignored. But for a growing number of applications, that's no longer possible. Even minor fluctuations in ... » read more

Fabs Begin Ramping Up Machine Learning

By Anne Meixner - 19 Dec, 2023 - Comments: 0

Fabs are beginning to deploy machine learning models to drill deep into complex processes, leveraging both vast compute power and significant advances in ML. All of this is necessary as dimensions shrink and complexity increases with new materials and structures, processes, and packaging options, and as demand for reliability increases. Building robust models requires training the algorithms... » read more

When And Where To Implement AI/ML In Fabs

By Anne Meixner - 21 Sep, 2023 - Comments: 0

Deciphering complex interactions between variables is where machine learning and deep learning shine, but figuring out exactly how ML-based systems will be most useful is the job of engineers. The challenge is in pairing their domain expertise with available ML tools to maximize the value of both. This depends on sufficient quantities of good data, highly optimized algorithms, and proper tra... » read more

Preventing Process Excursion With AI And Yield Management Software

By Krista Tropper - 09 May, 2023 - Comments: 0

Process excursion, or any deviation in a certain process, significantly impacts the cost of semiconductor manufacturing process and product yield. During production, process excursion can be detected early during in-line inspections. However, in some cases, excursion isn’t detected until later in the production process such as during wafer testing in the probing area after production. Apar... » read more

Using AI To Improve Metrology Tooling

By Laura Peters - 17 Apr, 2023 - Comments: 0

Virtual metrology is carefully being added into semiconductor manufacturing, where it is showing positive results, but the chip industry is proceeding cautiously. The first use of this technology has been for augmenting existing fab processes, such as advanced process control (APC). Controlling processes and managing yield generally do not require GPU processing and advanced algorithms, so t... » read more

Chip Manufacturing Data Now Requires Cloud Techniques

By Kenji Tsuda - 09 Dec, 2013 - Comments: 0

The parameters in semiconductor manufacturing are growing so large that an analysis method similar to what’s currently used for big data is now required. The good news is that big data analysis techniques, which process a vast amount of data such as search data and communication logs in the cloud, is entirely applicable to the data of semiconductor process. Photo 1: Opening view of AEC... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: advanced process control