Enhancing Compute Security Architecture For New-Age Applications

By Ajay Kapoor - 05 Dec, 2024 - Comments: 0

New-age AI-powered applications are becoming increasingly essential in our daily lives. Continuing to do so requires that these applications and services meet three primary challenges: Achieving high performance for complex compute tasks. Ensuring cost-effectiveness and seamless integration with existing infrastructure. Maintaining robust security and privacy measures. Historicall... » read more

Chiplet-Based NPUs to Accelerate Vehicular AI Perception Workloads

By Technical Paper Link - 02 Dec, 2024 - Comments: 0

A new technical paper titled "Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception" was published by researchers at UC Irvine. Abstract "We study the application of emerging chiplet-based Neural Processing Units to accelerate vehicular AI perception workloads in constrained automotive settings. The motivation stems from how chiplets technology i... » read more

Can You Rely Upon Your NPU Vendor To Be Your Customers’ Data Science Team?

By Steve Roddy - 12 Sep, 2024 - Comments: 0

The biggest mistake a chip design team can make in evaluating AI acceleration options for a new SoC is to rely entirely upon spreadsheets of performance numbers from the NPU vendor without going through the exercise of porting one or more new machine learning networks themselves using the vendor toolsets. Why is this a huge red flag? Most NPU vendors tell prospective customers that (1) the v... » read more

A HW-Aware Scalable Exact-Attention Execution Mechanism For GPUs (Microsoft)

By Technical Paper Link - 21 May, 2024 - Comments: 0

A technical paper titled “Lean Attention: Hardware-Aware Scalable Attention Mechanism for the Decode-Phase of Transformers” was published by researchers at Microsoft. Abstract: "Transformer-based models have emerged as one of the most widely used architectures for natural language processing, natural language generation, and image generation. The size of the state-of-the-art models has in... » read more

High-Level Synthesis Propels Next-Gen AI Accelerators

By Russell Klein - 20 May, 2024 - Comments: 0

Everything around you is getting smarter. Artificial intelligence is not just a data center application but will be deployed in all kinds of embedded systems that we interact with daily. We expect to talk to and gesture at them. We expect them to recognize and understand us. And we expect them to operate with just a little bit of common sense. This intelligence is making these systems not just ... » read more

Fallback Fails Spectacularly

By Steve Roddy - 16 May, 2024 - Comments: 0

Conventional AI/ML inference silicon designs employ a dedicated, hardwired matrix engine – typically called an “NPU” – paired with a legacy programmable processor – either a CPU, or DSP, or GPU. The common theory behind these two-core (or even three core) architectures is that most of the matrix-heavy machine learning workload runs on the dedicated accelerator for maximum efficienc... » read more

Research Bits: April 30

By Jesse Allen - 30 Apr, 2024 - Comments: 0

Sound waves in optical neural networks Researchers from the Max Planck Institute for the Science of Light and Massachusetts Institute of Technology found a way to build reconfigurable recurrent operators based on sound waves for photonic machine learning. They used light to create temporary acoustic waves in an optical fiber, which manipulate subsequent computational steps of an optical rec... » read more

Sea Of Processors Use Case

By Movellus - 27 Mar, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

A Hypermultiplexed Integrated Tensor Optical Processor (USC, MIT et al.)

By Technical Paper Link - 05 Mar, 2024 - Comments: 0

A technical paper titled “Hypermultiplexed Integrated Tensor Optical Processor” was published by researchers at the University of Southern California, Massachusetts Institute of Technology (MIT), City University of Hong Kong, and NTT Research. Abstract: "The escalating data volume and complexity resulting from the rapid expansion of artificial intelligence (AI), internet of things (IoT) a... » read more

AI Tradeoffs At The Edge

By Ann Mutschler - 15 Feb, 2024 - Comments: 0

AI is impacting almost every application area imaginable, but increasingly it is moving from the data center to the edge, where larger amounts of data need to be processed much more quickly than in the past. This has set off a scramble for massive improvements in performance much closer to the source of data, but with a familiar set of caveats — it must use very little power, be affordable... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.