Building Fixed HW Implementations of Neural Networks (Yale, Cornell et al.)


Researchers from Yale University, Cornell University, Boston University, and NTT Research have published “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”. Abstract "Foundation models are deep neural networks (such as GPT-5, Gemini~3, and Opus~4) trained on large datasets that can perform diverse downstream tasks -- text and code generation, q... » read more

Four Architectural Opportunities for LLM Inference Hardware (Google)


A new technical paper titled "Challenges and Research Directions for Large Language Model Inference Hardware" was published by Google. Abstract "Large Language Model (LLM) inference is hard. The autoregressive Decode phase of the underlying Transformer model makes LLM inference fundamentally different from training. Exacerbated by recent AI trends, the primary challenges are memory and in... » read more

Emerging Synaptic Memory Technologies For Neuromorphic CIM Platforms (Tampere Univ.)


A new technical paper titled "Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware" was published by researchers at Tampere University. Abstract: "The quest for energy-efficient, scalable neuromorphic computing has elevated compute-in-memory (CIM) architectures to the forefront of hardware innovation. While memristive... » read more

The Criticality of Performance per Watt Optimization for AI Chip Development


Chip developers are seeing an urgent rise in demand for compute processing capability driven by AI workloads. This increase in compute requirements drives a corresponding increase in the demand for power consumption. For example, a ChatGPT query requires nearly 10 times as much power, on average, as a Google search. Power has traditionally been treated as a secondary constraint, with perform... » read more

Building An AI Chip: Pre Silicon Planning


This white paper highlights the challenges of AI chip design, including balancing performance, cost, and power efficiency. It emphasizes the importance of early architecture exploration to avoid costly design revisions and ensure optimal power-performance trade-offs. The paper underscores the need for secure, efficient, and scalable IP solutions to meet the evolving demands of AI applications, ... » read more

All-In-One Analog AI Accelerator With CMO/HfOx ReRAM Integrated Into The BEOL (IBM Research-Europe)


A new technical paper titled "All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices" was published by researchers at IBM Research-Europe. Abstract "Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training accelera... » read more

Roadmap for AI HW Development, With The Role of Photonic Chips In Supporting Future LLMs (CUHK, NUS, UIUC, Berkeley)


A new technical paper titled "What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips" was published by researchers at The Chinese University of Hong Kong, National University of Singapore, University of Illinois Urbana-Champaign and UC Berkeley. Abstract "Large language models (LLMs) are rapidly pushing the limits of contemporary computing hardware. For example, t... » read more

Optimizing Data Movement


Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Getting Real About AI Processors


There’s a lot of confusion and hype around AI. Nearly every service, product or subject area in the technology industry now has an AI label. A lot of this is valid and there’s no doubt that AI is opening up new capabilities and higher productivity across all industries. This white paper categorises AI and related hardware options, with a particular focus on on-device (i.e. edge) AI, givi... » read more

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)


A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

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