Methodologies for accelerating convolutional neural networks (CNNs) using in-memory computing
Abstract:
“In-memory computing (IMC) is a non-von Neumann paradigm that has recently established itself as a promising approach for energy-efficient, high throughput hardware for deep learning applications. One prominent application of IMC is that of performing matrix-vector multiplication in (1) time complexity by mapping the synaptic weights of a neural-network layer to the devices of an IMC core. However, because of the significantly different pattern of execution compared to previous computational paradigms, IMC requires a rethinking of the architectural design choices made when designing deep-learning hardware. In this work, we focus on application-specific, IMC hardware for inference of Convolution Neural Networks (CNNs), and provide methodologies for implementing the various architectural components of the IMC core. Specifically, we present methods for mapping synaptic weights and activations on the memory structures and give evidence of the various trade-offs therein, such as the one between on-chip memory requirements and execution latency. Lastly, we show how to employ these methods to implement a pipelined dataflow that offers throughput and latency beyond state-of-the-art for image classification tasks.”
Access this open-access technical paper here. Published 08/2021.
Dazzi, M., Sebastian, A., Benini, L., & Eleftheriou, E. (2021, August 3). Accelerating inference of Convolutional Neural Networks using in-memory computing. Frontiers. Retrieved November 9, 2021, from https://www.frontiersin.org/articles/10.3389/fncom.2021.674154/full.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
Key pivot and innovation points in semiconductor manufacturing.
Thinner photoresist layers, line roughness, and stochastic defects add new problems for the angstrom generation of chips.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Less precision equals lower power, but standards are required to make this work.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
How customization, complexity, and geopolitical tensions are upending the global status quo.
127 startups raise $2.6B; data center connectivity, quantum computing, and batteries draw big funding.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
Leave a Reply