Improving Reliability In Automobiles


Carmakers are turning to predictive and preventive maintenance to improve the safety and reliability of increasingly electrified vehicles, setting the stage for more internal and external sensors, and more intelligence to interpret and react to the data generated by those sensors. The number of chips inside of vehicles has been steadily rising, regardless of whether they are powered by elect... » read more

GDDR6 Memory Enables High-Performance AI/ML Inference


A rapid rise in the size and sophistication of inference models has necessitated increasingly powerful hardware deployed at the network edge and in endpoint devices. To keep these inference processors and accelerators fed with data requires a state-of-the-art memory that delivers extremely high bandwidth. This blog will explore how GDDR6 supports the memory and performance requirements of artif... » read more

Weird Incidents Reveal L5 Challenges


A series of surprising, counterintuitive, and sometimes bizarre incidents reveal the challenges of achieving full Level 5 autonomy in self-driving vehicles, which are an increasingly common site in major cities. While it’s easy to dismiss such anecdotes as humorous glitches compared with the sobering accounts of autonomous tech-related injuries and fatalities, industry executives say these oc... » read more

Automated Optical Inspection


Building good automated models for inspection require more data to be collected, both good and bad. Vijay Thangamariappan, R&D engineer at Advantest, explains how to develop models for automating optical inspection, using a multi-thousand pin socket as an example for how machine learning has helped reduce the return rate due to defects from 2% down to zero. He also explains how to achieve t... » read more

Are We Too Hard On Artificial Intelligence For Autonomous Driving?


I recently attended and presented at Detroit's "Implementation of ISO 26262 & SOTIF" conference. Its subtitle was "Taking an Integrated Approach to Automotive Safety." After three days, my head was spinning with numbers of ISO/SAE and other standards. And at the end of day two, after yet another example that tricked autonomous driving prototypes into behaving wrongly, I sighed and asked whe... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam


Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Securing Accelerator Blades For Datacenter AI/ML Workloads


Data centers handle huge amounts of AI/ML training and inference workloads for their individual customers. Such a vast number of workloads calls for efficient processing, and to handle these workloads we have seen many new solutions emerge in the market. One of these solutions is pluggable accelerator blades, often deployed in massively parallel arrays, that implement the latest state-of-the-ar... » read more

Week In Review: Design, Low Power


Tools and IP Electronic system design revenue hit a record $3.75 billion in the second quarter, according to a report from ESD Alliance, a SEMI Technology Community. That number represents a 17.5% year-over-year increase. Walden C. Rhines, the report’s executive sponsor, said it was the largest such jump in over a decade and that all product categories and geographic regions recorded second ... » read more

Research Bits: Oct. 18


Modular AI chip Engineers at the Massachusetts Institute of Technology (MIT), Harvard University, Stanford University, Lawrence Berkeley National Laboratory, Korea Institute of Science and Technology, and Tsinghua University created a modular approach to building stackable, reconfigurable AI chips. The design comprises alternating layers of sensing and processing elements, along with LEDs t... » read more

HBM3 In The Data Center


Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

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