Who’s Calling The Shots

By Ann Mutschler - 31 Jul, 2015 - Comments: 0

Throughout the PC era and well into the mobile phone market, it was semiconductor companies that called the shots while OEMs followed their lead and designed systems around chips. That’s no longer the case. A shift has been underway over the past half decade, and continuing even now, to reverse that trend. The OEM — or systems company as it is more commonly called today — now determine... » read more

The Week In Review: Design/IoT

By Jesse Allen - 31 Jul, 2015 - Comments: 0

M&A ARM acquired Israel-based Sansa Security, a provider of hardware security IP and software for advanced system-on-chip components deployed in IoT and mobile devices. The company's technology is currently deployed across a range of smart connected devices and enterprise systems. Sansa IP will be integrated into ARM's TrustZone and IoT portfolios. Standards Accellera sent UVM 1.2 ... » read more

Accelerate SoC Simulation Time Of Newer Generation FPGAs

By Aldec - 29 Jul, 2015 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. To read more, click here. » read more

Blog Review: July 22

By Jesse Allen - 22 Jul, 2015 - Comments: 0

It's been a hot summer for high-level synthesis, says Cadence's Dave Pursley in a collection of the season's HLS highlights spanning DAC to SystemC Japan. Mentor's Harry Foster continues his survey of functional verification with a look at the adoption trends of various verification technologies, and the reasons one-third of projects use emulation or FPGA prototyping. Synopsys' Navraj Nan... » read more

UVM: What’s Stopping You?

By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Aldec

Who’s Calling The Shots

The Week In Review: Design/IoT

Accelerate SoC Simulation Time Of Newer Generation FPGAs

Blog Review: July 22

UVM: What’s Stopping You?