Silicon Photonics Manufacturing Ramps Up

By Gregory Haley - 21 Mar, 2024 - Comments: 0

Circuit scaling is starting to hit a wall as the laws of physics clash with exponential increases in the volume of data, forcing chipmakers to take a much closer look at silicon photonics as a way of moving data from where it is collected to where it is processed and stored. The laws of physics are immutable. Put simply, there are limits to how fast an electron can travel through copper. The... » read more

Package Integrated Vapor Chamber Heat Spreaders

By Sanghyuk Kim - 21 Mar, 2024 - Comments: 0

With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

UCIe Goes Back To The Drawing Board

By Gregory Haley - 22 Feb, 2024 - Comments: 0

The integration of multiple dies within a single package increasingly is viewed as the next evolution for extending Moore’s Law, but it also presents myriad challenges — particularly in achieving a universally accepted standard integrating plug-and-play chiplets from different vendors. “In some respects, people are already doing this,” says Debendra Das Sharma, Intel senior fellow an... » read more

Chip Industry Week In Review

By The SE Staff - 19 Jan, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Synopsys will acquire Ansys for about $35 billion in cash and stock. The deal will boost Synopsys' multi-physics simulation capabilities, which are essential for complex 3D-IC designs, where thermal density can have significant repercussions. The acquisition is expected to be finalized in the first half of 2025. Worldwide semiconductor revenue ... » read more

Elimination Of Die-Pop Defect By Vacuum Reflow For Ultrathin Die With Warpage In Semiconductor Packaging Assembly

By Amkor - 18 Jan, 2024 - Comments: 0

Semiconductor die thickness is getting thinner over time due to improvement of power efficiency in advance power electronic packages. Ultrathin die with convex warpage can easily deteriorate the solder void removal process during solder reflow, leading to various packaging reliability issues. In particular, a new type of packaging defect phenomenon—die-pop—is observed. Vacuum reflow process... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging

By JiHye Kwon - 18 Jan, 2024 - Comments: 1

The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

Plugging Gaps In The IC Supply Chain

By Anne Meixner - 09 Jan, 2024 - Comments: 0

Multiple touch points in manufacturing and packaging are exposing gaps in the data used to track different components, making it difficult to identify the source of issues that can affect yield and reliability, and opening the door to counterfeit or sub-standard parts. This involves more than just assigning a simple identifying code to a chip. At different points in a device's lifecycle, new... » read more

Money Pours Into New Fabs And Facilities

By Liz Allan - 03 Jan, 2024 - Comments: 0

Fabs, packaging, test and assembly, and R&D all drew major funding in 2023. Companies poured money into offshore locations, such as India and Malaysia, to access a larger workforce and lower costs, while also partnering with governments to secure domestic supply chains amid ongoing geopolitical turmoil. Looking ahead, artificial intelligence (AI), quantum computing, and data applications... » read more

Proprietary Vs. Commercial Chiplets

By Ed Sperling - 19 Dec, 2023 - Comments: 0

Large chipmakers are focusing on chiplets as the best path forward for integrating more functions into electronic devices. The challenge now is how to pull the rest of the chip industry along, creating a marketplace for third-party chiplets that can be chosen from a menu using specific criteria that can speed time to market, help to control costs, and behave as reliably as chiplets developed in... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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Partitioning In The Chiplet Era

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by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.