tag: analog design

Managing Analog Designs For Successful Tapeouts
By Cliosoft - 06 Nov, 2019 - Comments: 0

Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

Why Analog Designs Fail
By Brian Bailey - 14 Feb, 2019 - Comments: 2

The gap between analog and digital reliability is growing, and digital designs appear to be winning. Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren't always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuit... » read more

How To Improve Analog Design Reuse
By Ann Mutschler - 14 Nov, 2018 - Comments: 0

Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more

Body Biasing For Analog Design
By Fraunhofer IIS/EAS - 13 Dec, 2017 - Comments: 0

This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the trade- off between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three dif... » read more

Speeding Up Analog
By Ann Mutschler - 05 Aug, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Speeding Up Analog
By Ann Mutschler - 16 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Speeding Up Analog
By Ann Mutschler - 09 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss analog design and how to speed it up with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What follows are excer... » read more

Filling In The Gaps For Mixed-Signal Verification
By Ann Mutschler - 31 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal verification with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at [getentity id="22035" comment="Synopsys"]. What follows are excerpts of t... » read more

The New Mixed-Signal Flow
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler We are on the cusp of the mixed-signal era. Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, no longer are sufficient. They lead to excess iteration and prolonged design cycle time. Today’s mixed-signal designs require a new approach that enables design teams to be as efficient as possible productivity... » read more

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

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