tag: analog

Solving The Memory Bottleneck
By Brian Bailey - 04 Oct, 2019 - Comments: 4

Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

Getting To Tape-Out Quicker With Analog Layout Generators
By Benjamin Prautsch - 08 Aug, 2019 - Comments: 0

All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

200mm Cools Off, But Not For Long
By Mark LaPedus - 18 Jul, 2019 - Comments: 4

After years of acute shortages, 200mm fab capacity is finally loosening up, but the supply/demand picture could soon change with several challenges on the horizon. 200mm fabs are older facilities with more mature processes, although they still churn out a multitude of today’s critical chips, such as analog, MEMS, RF and others. From 2016 to 2018, booming demand for these and other chips ca... » read more

From Constraints to Tape-Out: Towards A Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 15 Jul, 2019 - Comments: 0

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Aspinity’s Analog Neural Net Wake-Up Call
By Susan Rambo - 26 Jun, 2019 - Comments: 0

Putting an analog chip in front of an always-on system for digitizing speech and having the analog chip listen for sounds of interest may help avoid huge power waste and data congestion in current voice-recognition systems. Aspinity, an analog neuromorphic semiconductor startup, has worked the problem and just announced its Reconfigurable Analog Modular Processor (RAMP) platform yesterday. RAMP... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War
By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Automotive Semiconductors Boost MCU, Analog Markets
By Jim Feldhan - 20 Jun, 2019 - Comments: 0

Auto sales are expected to experience a slowdown in 2019, and even with the continued increase in electronics per vehicle, automotive semiconductor sales are also expected to experience a slowdown. Similar to prior years, 2019/2020 car models will include more automotive semiconductor devices to provide higher degrees of safety, comfort and convenience, driver assist capabilities, in-cabin ente... » read more

Revolution By Evolution: Getting To The Next Technology Breakthrough In Analog Simulation
By Cadence - 12 Jun, 2019 - Comments: 0

Recent technology developments, advanced-node adoptions, and Moore than Moore designs have forced analog and custom IC designers to adopt new design practices that benefit from these advancements. These changes have resulted in the need to simulate larger designs with more post-layout parasitics. In addition, many custom IC designs such as flash memory, MRAM, sensor arrays, etc., now require SP... » read more

From Constraints To Tape-Out: Towards A Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 12 Jun, 2019 - Comments: 0

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

Holes In AI Security
By Ed Sperling - 06 Jun, 2019 - Comments: 0

Mike Borza, principal security technologist in Synopsys’ Solutions Group, explains why security is lacking in AI, why AI is especially susceptible to Trojans, and why small changes in training data can have big impacts on many devices. » read more

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