Solutions For Mixed-Signal IP, IC, And SoC Implementation

By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Over 50% Of Smart Phones And Tablets Leverage SOI

By Various Writers - 18 Mar, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ In a recent press release, the SOI wafer leader Soitec said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. 50%? That’s a lot! How do they figure that? The answer: RF. [caption id="attachment_809" align="alignleft" width="549" caption="As seen here... » read more

Smarter Things

By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous. There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is... » read more

Raising The Stakes For IP

By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Taming The Challenges Of 20nm Custom/Analog Design

By Various Writers - 29 Nov, 2012 - Comments: 0

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers. To view this white paper, click here. » read more

Experts At The Table: Obstacles In Low-Power Design

By Ed Sperling - 16 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What effe... » read more

Mixed-Signal IP Design Challenges In 28nm Process And Beyond

By Various Writers - 23 Aug, 2012 - Comments: 0

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes. This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of ... » read more

Analog Hits The Power Wall

By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Analog design teams are starting to encounter the same physical issues that digital design engineers began wrestling with several nodes ago—only the problems are more complicated and even more difficult to solve. At advanced nodes digital circuitry is susceptible to an array of physical effects ranging from heat, electromigration, electromagnetic interference and electrosta... » read more

Analog In The 300mm Era

By Adrienne Downey - 31 Jul, 2012 - Comments: 0

By Adrienne Downey Semico forecasts the 2012 analog market will grow 5.1% to $44.5 billion, up from $42.3 billion in 2011. This is higher than the 0.1% analog revenue growth experienced in 2011 but lower than the 12.6% growth expected in 2013. Growth is coming from automotive electronics, the energy industry, wireless communications, and healthcare diagnostic and monitoring devices. In a re... » read more

The Challenges Of 28nm HKMG

By Various Writers - 26 Jun, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt's (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performanc... » read more

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Knowledge Centers
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