How Many Cores? (Part 1)


The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

Getting Ready For The IoT


A major change is underway in the semiconductor industry, and it is being driven by the Internet of Things. Gartner defines the IoT as a “network of dedicated physical objects (things) that contain embedded technology to sense or interact with their internal state or external environment. The IoT comprises an ecosystem that includes things, communication, applications and data analysis.” ... » read more

The Week In Review: Design/IoT


Know someone who deserves the Phil Kaufman Award for Distinguished Contributions to EDA? Nominations are open until June 30th. Tools, IP & Chips ARM debuted the Cortex-R8 processor, targeting mass storage devices and future 5G modems with a quad-core configuration and extended low-latency memory. Cadence's schematic design tool, OrCAD Capture, added the capability to export hierarc... » read more

The Week In Review: Design/IoT


NXP received all necessary regulatory approvals for the merger with Freescale, and the sale of its RF Power business to JAC Capital. The company now expects to close the merger on December 7. Synopsys introduced VIP to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard. The VIP includes a native SystemVerilog UVM architecture, protocol-aware debug and source code test suites. ... » read more

The Week In Review: Design/IoT


Predictions Wally Rhines, Mentor Graphics' chairman and CEO, was presented with the Kaufman Award last night for outstanding achievement in electronic design. In his acceptance speech, he plotted the growth of the EDA industry at a consistent 2% of the semiconductor industry for the past couple decades. But he noted that with a shift to system design automation, that number would rise from t... » read more

The Week In Review: Design/IoT


Mentor Graphics began selling infrastructure hardware this week, including an end-to-end IoT solution that includes a reference design for a customizable gateway, a cloud backend, and runtime solutions on which to build a wide array of IoT edge devices. Mentor also released virtual platforms for Altera's Arria 10 SoC FPGA, and updated its Valor PCB manufacturing process to focus on Industry 4.0... » read more

Security In 2.5D


The long-anticipated move to 2.5D and fan-outs is raising some familiar questions about security. Will multiple chips combined in an advanced package be as secure as SoCs where everything is integrated on the same die? The answer isn't a simple yes or no. Put in perspective, all chips are vulnerable to [getkc id="253" kc_name="side channel attacks"], hacking of memory—a risk that increases... » read more

The Rise Of Dynamic Networks


The Internet of the future, and particularly the [getkc id="260" comment="Internet of Everything"], will be interlaced with millions if not billions of intelligent, dynamic, self-organizing networks. These networks will be full of elements that are capable of autonomic self-registration across these multitudes of networks. It is one thing to put up a security perimeter when you know who the... » read more

Metrics For Measuring Performance And Power In IoT SoC Designs


The problem confronting chip designers developing IoT SoCs is the need for high compute performance and low power consumption. This is especially true for SoCs being developed for devices required to operate for years on a battery. One example is the new generation of electronic shelf label (ESL) with a requirement of five years. The ESL receives central server pricing updates along with a f... » read more

Appetite For Services Grows


Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

← Older posts Newer posts →