Chip Industry Week In Review


By Susan Rambo, Karen Heyman, and Liz Allan The Biden-Harris administration designated 31 Tech Hubs across the U.S. this week, focused on industries including autonomous systems, quantum computing, biotechnology, precision medicine, clean energy advancement, and semiconductor manufacturing. The Department of Commerce (DOC) also launched its second Tech Hubs Notice of Funding Opportunity. ... » read more

Anatomy Of A System Simulation


The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

Blog Review: October 25


Synopsys’ Graham Allan looks at enhancements in the LPDDR5X standard, such as a speed increase from 6.4Gbps to 8.5Gbps using the same 1.1V core voltage as LPDDR5 alongside better signal integrity, reliability, and battery efficiency. Cadence’s Krunal Patel examines the essential components and operation of MACsec, a security protocol to ensure the confidentiality and integrity of data tr... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan SRC unfurled its Microelectronics and Advanced Packaging (MAPT) industry-wide 3D semiconductor roadmap, addressing such topics as advanced packaging, heterogeneous integration, analog and mixed-signal semiconductors, energy efficiency, security, the related foundational ecosystem, and more. The guidance is the collective effort of 300 individuals ... » read more

Blog Review: October 18


Siemens' Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design. Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, a... » read more

Chip Industry Talent Shortage Drives Academic Partnerships


Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Partitioning Processors For AI Workloads


Partitioning in complex chips is beginning to resemble a high-stakes guessing game, where choices need to extrapolate from what is known today to what is expected by the time a chip finally ships. Partitioning of workloads used to be a straightforward task, although not necessarily a simple one. It depended on how a device was expected to be used, the various compute, storage and data paths ... » read more

Automating Antenna Placement Workflow With PyAEDT


Antenna designs can reach daunting levels of complexity, and nowhere is that truer than in advanced 5G and 6G systems. One of the most difficult problems in this design space is signal degradation stemming from electromagnetic (EM) interaction between the phased array antenna and the host structure itself, such as a base station or satellites. It is a pernicious issue that takes several advance... » read more

Maximizing Design Flexibility For Multi-Layered And Diffractive Optical Components


A broad range of optical devices use nanostructured layers and surfaces to manipulate beams of light through diffraction and interference. Example devices include diffraction gratings, metasurfaces, diffractive optical elements, and metalenses. While the purpose and function of these devices can differ, they offer similar challenges from the point of view of simulation. In this white paper, ... » read more

Blog Review: October 11


Cadence's Sangeeta Soni examines Integrity and Data Encryption (IDE) verification considerations for Compute Express Link (CXL) devices, including MAC generation and handling, key programming and exchange, and early MAC termination. Synopsys' Madhumita Sanyal points to how the increased bandwidth of PCIe 6.0 supports the demanding requirements of AI accelerators. Siemens' Kevin Webb expla... » read more

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