tag: ANSYS

How To Build Resilience Into Chips
By Ed Sperling and Ann Mutschler - 27 Feb, 2023 - Comments: 0

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Taming Corner Explosion In Complex Chips
By Brian Bailey - 23 Feb, 2023 - Comments: 0

There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

Blog Review: Feb. 22
By Jesse Allen - 22 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster observes that the FPGA market continues to go through a similar complexity curve that the IC/ASIC market experienced in the early and mid-2000 timeframe. Synopsys' Mitch Heins explores the benefits of heterogeneous integration of lasers and active gain elements in a silicon-based photonic IC, including reduced system costs, size, weight, and power along with improv... » read more

Blog Review: Feb. 15
By Jesse Allen - 15 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Feb, 2023 - Comments: 0

Arm is heading for an IPO this year, with plans "fairly well developed and underway now," CEO Rene Haas told Reuters. Arm reported fiscal Q3 revenue of $746 million, up 28% compared with the same period in 2021, setting the stage for a public offering. The company noted it had double- or triple-revenue increases in automotive, consumer, infrastructure, and IoT. The Si2 Compact Model Coalit... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 10 Feb, 2023 - Comments: 0

General Motors (GM) made a deal with GlobalFoundries (GF) to have chips made at the U.S.-based foundry in upstate New York for GM’s key suppliers. GF will expand its production capabilities exclusively for GM’s supply chain, while GM promises to bring economies of scale through its strategy to reduce the unique types of chips needed in products. J.D. Power released its 2023 U.S. Vehicle ... » read more

Chiplets Taking Root As Silicon-Proven Hard IP
By Ann Mutschler - 09 Feb, 2023 - Comments: 0

Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Simulating Reality: The Importance Of Synthetic Data In AI/ML Systems For Radar Applications
By Arien Sligar - 09 Feb, 2023 - Comments: 0

Artificial intelligence and machine learning (AI/ML) are driving the development of next-generation radar perception. However, these AI/ML-based perception models require enough data to learn patterns and relationships to make accurate predictions on new, unseen data and scenarios. In the field of radar applications, the data used to train these models is often collected from real-world meas... » read more

Blog Review: Feb. 8
By Jesse Allen - 08 Feb, 2023 - Comments: 0

Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Best Practice: RANS Turbulence Modeling In Ansys CFD
By Ansys - 08 Feb, 2023 - Comments: 0

Turbulence modeling is one of the main sources of uncertainty in CFD simulations of technical flows. This is not surprising, as turbulence is the most complex phenomenon in classical physics. Turbulent flows pose a multi-scale problem, where the dimension of the technical device is often of the order of meters (or even 102 meters in case of airplanes and ships), whereas the smallest turbulence ... » read more

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