Week In Review: Semiconductor Manufacturing, Test

Further restrictions on China; ASML boosts imec’s pilot line; JSR is purchased; UMC-Metalenz deal; EU, Japan may share investing plans; Samsung Foundry certifications.


Restrictions on China continue to grow. The Biden Administration is considering more restrictions on selling advanced AI chips to China, according to multiple media reports. Meanwhile, the Dutch government is expected to limit the sale of manufacturing equipment.

JIC Capital, the wholly owned subsidiary of Japan Investment Corporation (JIC), will purchase materials company JSR Corp. through a tender offer of 903.9 billion yen ($6.3 billion). JSR supplies photoresist, other materials and equipment for semiconductor manufacturing and packaging. JIC is backed by the Japanese government.

ASML and imec signed a memorandum of understanding (MOU) to boost their collaboration and specifically to install and service ASML’s advanced lithography and metrology equipment in the imec pilot line in Leuven, Belgium.

UMC’s 12-inch wafer fab in Singapore will start producing Metalenz’s metasurface optics. Metalenz, founded in 2016, says it is the first company to commercialize meta-optics, a experimental type of optics used in 3D depth-sensing design. The move launches metasurface optics on the open market. UMC will expand its offering into meta-optics.

CEA-Leti will develop sub-10nm node FD-SOI chips with a new non-volatile onboard memory as part of its NextGen fab project. Following its lab-to-fab model, CEA research lab will be built as a cleanroom equipped with the latest semiconductor machines that fabs typically use in production lines to make it easier to commercialize new chips. CEA expects it will hire 200 employees in the Grenoble area for the project. FD-SOI components, which use a silicon substrate with a buried oxide insulating layer, are currently fabricated at 28nm and 22nm by several semiconductor manufacturers.

FD-SOI transistor. Source: CEA-Leti (La mama studio)

Fig. 1.  CEA-Leti’s FD-SOI. Source: CEA-Leti/La Mama Studio

Japan and the European Union will share information about their semiconductor investment, according to a story in Nikkei Asia. The United States is also in an information sharing agreement with Japan and the EU — sharing investment information is a way to avoid over investing, the story claims, which could destabilize some markets.

Wolfspeed received $1.25 billion secured note financing from an investment group led by Apollo to support the company’s expansion and development of silicon carbide (SiC) products. The financing includes up to an additional $750 million. Just under 10% of the notes will be due in 2030.

Shift left, verification, and test

Announcements from the Samsung Advanced Foundry Ecosystem (SAFE) Forum North America 2023 highlighted the newest Samsung Foundry — EDA certifications.

Samsung also certified Ansys’ multiphysics power integrity and 3D-IC thermal integrity platform for Samsung Foundry’s X-Cube technology for 3D packaging, the company’s heterogeneous multi-die packaging technologies, and the foundry certified Ansys on its 2nm process technology.

Ansys and Synopsys have a new reference flow for RFIC design for Samsung 14LPU technology, putting together Ansys’ golden signoff electromagnetic analysis and Synopsys’ analog/RF and mixed-signal design and verification.

Siemens’ Calibre nmPlatform is now certified for Samsung’s 3nm (with 2nm in the works). Siemens Analog FastSPICE (AFS) platform is also approved for use on Samsung Foundry’s FD-SOI 18FDS process technology, and its FinFET, EUV, and GAA fabrication processes. Siemens and Samsung also have successfully demonstrated a consolidated Design for Test (DFT) flow using Siemens’ Tessent Multi-die software for 3D IC designs, among other achievements.

Samsung Foundry certified Cadence Virtuoso Studio Flow for node-to-node design and layout migration. The Studio is powered by generative AI. Samsung also certified Cadence’s digital and custom/analog design flows for Samsung Foundry’s SF2 and SF3 process tech, and Cadence’s AI-based Cadence Virtuoso Studio design tools and solutions have been certified.

Before a new device makes it to high-volume manufacturing, countless engineering hours are spent on developing the lithography, etching, deposition, CMP, and many other processes, at high yield. Device fabrication requires as many as 1,000 individual tool steps. But what challenges engineers most is the need to meet process specifications with nanometer level precision, which can lengthen development times and increase cost.


Samsung Foundry adopted Keysight’s IC-CAP Model Generator (MG), which will be used to create circuit libraries for PDKs for Samsung’s advanced radio frequency (RF) semiconductor process technologies.

Bruker announced a new benchtop X-ray diffraction (XRD) platform for materials analysis and research. The D6 PHASER has the functionality of the floor-standing D8 but in a compact model.


Researchers from Clemson University developed a 2D electrically conductive metal-organic framework (MOF) that has a higher has conductivity (by 10- to 15-times) than the current MOF.


  • SEMICON China, June 29 – July 1
  • SEMICON West 2023, San Francisco, Calif., July 11 – 13
  • SPIE Optics and Photonics, San Diego, Aug 20-24
  • DARPA: Electronics Resurgence Initiative, Seattle, Aug 22-24

For more events, go to our event page.

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