Week In Review: Design, Low Power


Nvidia acquired Oski Technology. Oski provides formal verification methodologies and consulting services, and Nvidia said that the acquisition will allow it to increase its investment in formal verification strategies. Oski's Gurugram, India, design center will become Nvidia's fourth engineering office in the country. Based in San Jose, Calif., it was founded in 2005. Terms of the deal were not... » read more

Architecting Interposers


An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

How To Identify Common Electronic Failures


Failure analysis is the process of identifying, and typically attempting to mitigate, the root cause of a failure. In the electronics industry, failure analysis involves isolating the failure to a location on a printed circuit board assembly (PCBA) before collecting more detailed data to investigate which component or board location is functioning improperly. A member of the Ansys Reliabil... » read more

Will Co-Packaged Optics Replace Pluggables?


As optical connections work their way deeper into the data center, a debate is underway. Is it better to use pluggable optical modules or to embed lasers deep into advanced packages? There are issues of convenience, power, and reliability driving the discussion, and an eventual winner isn’t clear yet. “The industry is definitely embracing co-packaged optics,” said James Pond, principal... » read more

Bringing Intelligent Headlamps To Light via Simulation


Once seen as a basic, utilitarian product feature, today automotive headlamps are becoming much more innovative — and a critical source of competitive differentiation. Intelligent headlamps, which autonomously produce adaptive light beams, are capturing the imagination of the world’s automakers and consumers alike. But how can automotive engineering teams verify the performance of their com... » read more

Blog Review: Oct. 13


Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

PCB And IC Technologies Meet In The Middle


Surface-mount technology (SMT) is evolving far beyond its roots as a way of assembling packaged chips onto printed circuit boards without through-holes. It is now moving inside packages that will themselves be mounted on PCBs. But SMT for advanced packages isn’t the same as the SMT we’ve been used to. “Many systems include multiple ASICs, a lot of memory, and that's all integrated i... » read more

Week In Review: Design, Low Power


Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Qualcomm and SSW Partners, an investment partnership, now have a definitive agreement to acquire advanced driver assistance systems (ADAS) company Veoneer for $37.00 per share in an all-cash transaction that equals $4.5 billion in equity value. A few months ago, Qualcomm made the proposal to Veoneer after the company already had an agreement in place with Magma, a 60-year-old automo... » read more

Blog Review: Oct. 6


Arizona State University's Jae-sun Seo and Arm's Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights. Cadence's Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance... » read more

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