Chip Industry Week in Review


Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Blog Review: July 31


Cadence's Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs. Synopsys' Robert Fey finds that by automatically and dynamically linking requirements a... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Will AI Disrupt EDA?


Generative AI has disrupted search, it is transforming the computing landscape, and now it's threatening to disrupt EDA. But despite the buzz and the broad pronouncements of radical changes ahead, it remains unclear where it will have impact and how deep any changes will be. EDA has two primary roles — automation and optimization. Many of the optimization problems are NP hard, which means ... » read more

Chip Industry Week In Review


The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

Heat-Related Issues Impact Reliability In Advanced IC Designs


Heat is becoming a much bigger problem in advanced-node chips and packages, causing critical electrons to leak out of DRAM, timing and reliability issues in 3D-ICs, and accelerated aging that are unique to different workloads. All types of circuitry are vulnerable to thermal effects. It can slow the movement of the electrons through wires, cause electromigration that shortens the lifespan of... » read more

Data Center Thermal Management Improves


Thermal issues are plaguing semiconductor design at every level, from chips developed with single-digit nanometer processes to 100,000-square-foot data centers. The underlying cause is too many devices or services that require increasing amounts of power, and too few opportunities for the resulting heat to dissipate. “Everybody wants to try to do more in a small volume of space,” said St... » read more

IC Power Optimization Required, But More Difficult To Achieve


Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

How Simulation Addresses Hydrogen Fuel Challenges


By Kiyoung Jung and Kyutae Kim Hydrogen has gained the front seat as a fuel for carbon neutrality. The absence of carbon emission at the point of utilization makes it attractive for net-zero initiatives. Hydrogen fuel possesses qualities like higher flame speed (8x higher), lower ignition energy requirements (15x lower), and wider flammability limit (4% to 70%) compared to typical hydrocar... » read more

Blog Review: July 17


Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

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