tag: ANSYS

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2024 - Comments: 0

Cadence's Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host's CPU to reduce latency and improve overall system performance. Synopsys' John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the ... » read more

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Chip Industry Week In Review
By The SE Staff - 08 Mar, 2024 - Comments: 0

By Adam Kovac, Gregory Haley, and Liz Allan. Cadence plans to acquire BETA CAE Systems for $1.24 billion, the latest volley in a race to sell multi-physics simulation and analysis across a broad set of customers with deep pockets. Cadence said the deal opens the door to structural analysis for the automotive, aerospace, industrial, and health care sectors. Under the terms of the agreement, 6... » read more

V2X Path To Deployment Still Murky
By Ann Mutschler - 07 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss Vehicle-To-Everything (V2X) technology and the path to deployment, with Shawn Carpenter, program director for 5G and space at Ansys; Lang Lin, principal product manager at Ansys; Daniel Dalpiaz, senior manager product marketing, Americas, green industrial power division at Infineon; David Fritz, vice president of virtual and hy... » read more

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2024 - Comments: 0

Synopsys' Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing. Cadence's John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human e... » read more

Chip Industry Week In Review
By The SE Staff - 01 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

2.5D Integration: Big Chip Or Small PCB?
By Brian Bailey - 29 Feb, 2024 - Comments: 1

Defining whether a 2.5D device is a printed circuit board shrunk down to fit into a package, or is a chip that extends beyond the limits of a single die, may seem like hair-splitting semantics, but it can have significant consequences for the overall success of a design. Planar chips always have been limited by size of the reticle, which is about 858mm2. Beyond that, yield issues make the si... » read more

Blog Review: Feb. 28
By Jesse Allen - 28 Feb, 2024 - Comments: 0

Synopsys' Emilie Viasnoff suggests that employing virtual sensors when developing an autonomous driving system helps aid in sensor design and minimizes the hazards associated with extensive real-world driving. Cadence's Anthony Ducimo introduces a methodology for embedded BootROM verification that relies only on standard RTL verification toolchains to reveal bugs, identify unused sections of... » read more

Chip Industry Week In Review
By The SE Staff - 23 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

Blog Review: Feb. 21
By Jesse Allen - 21 Feb, 2024 - Comments: 0

Siemens' John McMillan digs into physical verification maturity for high-density advanced packaging (HDAP) designs and major differences in the LVS verification flow compared to the well-established process for SoCs. Synopsys' Varun Shah identifies why a cloud adoption framework is key to getting the most out of deploying EDA tools in the cloud, including by ensuring that different types of ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy