Navigating The Challenges Of Group Design Projects


All over the world, governments and industry have come together to solve large-scale chip design challenges. Groups such as the U.S. Department of Defense’s Microelectronics Hubs (ME Commons), the EU Chips Act pilot lines, and Japan’s government-backed Rapidus consortium often consist of established companies, research institutes, academia, and startups – each of which brings different sk... » read more

The Limits Of AI’s Role In EDA Tools


The world has been inspired by generative AI models like ChatGPT. These are very applicable to things like copilots and agentic AI, but the adoption of these models into EDA tools is less obvious. What may be appropriate, and can AI make EDA tools faster or better? EDA has been enabling Moore's Law for the past 40 years, and that has required pushing the limits of many of the algorithms and ... » read more

Blog Review: Sept. 24


Siemens' Harry Foster warns of a big drop in first-time silicon success as more system companies tackle developing their own chip without the accumulated knowledge around flows, sign-off criteria, and coverage closure in a landscape where even small oversights in methodology can lead to multimillion-dollar respins. Synopsys' Godwin Maben warns that skyrocketing power consumption is a critica... » read more

Blog Review: Sept. 17


Siemens' John McMillan explores the fundamentals of IC package thermal resistance, modeling strategies, and why die-level thermal analysis in 3D-ICs is increasingly essential for ensuring device reliability. Cadence's Jasmine Makhija provides an overview of the TEE Device Interface Security Protocol (TDISP), which helps safeguard PCIe devices within Trusted Execution Environments by providin... » read more

New Antennas And Advanced ICs Needed For 6G


6G is expected to bring data speeds that enable highly integrated and responsive technology in smartphones, homes, cities, and autonomous vehicles, but realizing that goal will require a lot more work. There will be many more antennas everywhere, embedded in infrastructure around town, in base stations, edge-devices, and everything in between. They will be sending and receiving many more sig... » read more

Balancing Workloads In AI Processor Designs


A growing number of AI processors are being designed around specific workloads rather than standardized benchmarks, optimizing performance and power efficiency, but often with enough flexibility to adapt to future changes. While the fundamentals of matrix multiplication and software optimization still apply, those alone are no longer sufficient. Designs need to address specific data types, w... » read more

Coloring Optical Signals For More Bandwidth In Data Centers


Copper cabling has been the workhorse for moving data inside of AI and HPC data centers, but fiber is nipping at its heels. Optics brings three possible bandwidth multipliers — wavelength-division multiplexing (WDM), the use of different modes, and polarization. Each has a role in longer-distance optical links, but the tradeoffs are different in the data center. WDM appears poised to boost... » read more

The Demise Of Static Timing Verification?


The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Modern Factories Thrive By Manufacturing Smarter With Simulation


By Jennifer Procario and Peter Slättman Automation induces anxiety in those who fear that technology will replace humans in the workforce. But as we transition from Industry 4.0 to 5.0, some apprehension could be alleviated with a shift in focus. The fourth industrial revolution centered on technology, but the fifth emphasizes human interaction and collaboration with technology. The Europ... » read more

Blog Review: Sept. 10


Cadence's Satish Kumar C explains Port-Based Routing, a feature in in CXL 3.0 and 3.1 that changes how CXL switches operate within a CXL fabric to enable the creation of much larger, more flexible, and more efficient topologies. Siemens' Bill Hargin demystifies copper foil thickness and weight measurements and why being precise has an impact on signal integrity and crosstalk simulations.... » read more

← Older posts Newer posts →