As more companies and startups join forces with government and academia in chip design projects, issues around data sharing, IP protection, and PDK access must be solved.
All over the world, governments and industry have come together to solve large-scale chip design challenges. Groups such as the U.S. Department of Defense’s Microelectronics Hubs (ME Commons), the EU Chips Act pilot lines, and Japan’s government-backed Rapidus consortium often consist of established companies, research institutes, academia, and startups – each of which brings different skill sets to the equation.
In this setting, the chip design community is accelerating, scaling up, and taking risks that they might not have taken without government funding, said Nilesh Kamdar, general manager, design and verification business unit at Keysight Technologies, which is involved with many of the DoD’s ME Commons and recently partnered with Rapidus to develop a high-precision process design kit (PDK). “The Commons is a great way to take this to all the regional entities. There are eight different entities, and six different technology areas that we’re focused on. It wasn’t initially clear how ME Commons would be set up, but having regional centers of excellence, where several universities lead and bring together a partnership of universities, commercial groups, and various ecosystem players like EDA vendors, has been very interesting.”
However, there are several key challenges to group design projects, which are further complicated if government funding is involved:
IP management and monetizing a product
While the initial intent of a project may be for everyone involved to benefit, that does not solve the problem of how each company will be compensated if and when a product hits the market.
“If you are working to develop something new in a group effort, who owns what’s developed?” said Nick Kepler, COO at startup incubator Silicon Catalyst. “Does everybody own it? Does somebody own this piece of it? Does somebody own this other piece of it? I think the way this works best is if you can get combinations that are pre-competitive.”
Companies have been working together to develop process technologies and components for some time, but design tools bring different challenges.
“The question of IP management and data management is huge,” Kamdar. “I don’t think anybody has clearly solved this problem. If I were a semiconductor company and came across some very interesting AI technologies that allowed me to accelerate my semiconductor lifecycle, how would I use it? Can I use it from one project to another? Can I let it be trained on my own designs and then use it on my next design? Is that something that I want to do? That’s the promise. If you do that, you can benefit. Can we do this as an industry? I don’t think we’ve answered that question. Potentially, universities could do that. Universities may have IP that they could train and decide that they’re going to share with other universities.”
Likewise, companies within government programs can figure out a way to share data and IP. “But the promise is always that the IP is owned by the team or the company that’s doing the design, and each stays on-prem,” said Kamdar. “We can explore different ways of how to monetize this. But at this point, it’s a pretty good concern, especially if you look at use cases such as government or aerospace, there’s even more demands on IP protection there.”
Companies working with government agencies need to find the best way to foster innovation and collaboration while protecting IP.
“Part of this is the evolution of these things, to find the right niche to work,” said Saverio Fazzari, senior lead engineer, engineering fellow for microelectronics at Booz Allen, on a DAC panel. [1] “The IP protection piece is a critical part of it, and developing an IP model that enables that innovative research. My experience is that if you address it up front, you will be successful. If you wait, it prevents that success as those projects become contained, and you don’t get that sharing and innovation. What we’re seeing now within the Commons are people starting to figure out how to make that happen the right way. From there, the challenge will be, as you move forward, how does that become a product, and how do you deal with that stuff? I know particular organizations that have IP lawyers and other people in place to figure out what that model looks like. Because ultimately, for many of those folks, it’s okay, ‘How am I going to make money off of this thing as I go forward with this?’ That’s still a challenge to figure out. From an R&D perspective, it’s great. We’ve achieved our goal.”
How to make money from group innovation is a multi-billion-dollar question, agreed Vivek Prasad, vice president of design engineering ecosystem enablement at Natcast, on the same panel. “It’s still not a solved problem. You have to look at research from a pre-competitive space first, where you really need collaboration, not only within the US, but across the world. Pre-competitive collaboration needs to happen to really further our technological capabilities. Then, once you start to get into the competitive space, funding is needed to support the technologies that are coming five years from now. How do you measure them? This is where we need the collective.”
Silicon Catalyst’s Kepler points to his time spent working on next-generation process technology at AMD as an example of how pre-competitive collaboration can work. “We did more than one partnership with other companies to develop the technology, and we would all work jointly on the technology, and we would all have the rights to the jointly developed technology but would each transfer it independently to our own manufacturing facilities and put our own product designs into it. We were competing with independent designs and independent factories, but we had the same base technology; that’s not what we competed with each other on.”
Startups also benefit from pre-competitive innovation, whether that happens at universities or as part of a government program.
“There isn’t a commercial competition amongst universities, but that research can then be taken by different companies and turned into a commercial offering,” said Kepler. “A lot of startups that come to us are coming out of research that’s happened in a university, and they’re trying to take that research and the results they’ve received, and have been able to get a PhD and publish a paper, and now they’re trying to turn it into a profitable company. It’s the same on the path of research and government funding. You could have three or four different entities take that same research and try to do different things with each other, and maybe compete with each other. But the basic research was funded by the government to provide the ability for all of those commercial things to happen. I think that’s a really good model, not only for research in manufacturing technologies and in design technologies, but also in electronic design automation, which is an area that hasn’t gotten as much attention, and all of those things are really, really valuable to an economy.”
Benefits, challenges of data sharing
In an era when data is considered the new gold, companies are figuring out how much they want to share, especially when it comes to developing AI and EDA tools. AI models benefit from being trained on real data, and this feeds into the efficacy of the EDA tools. But because of proprietary IP, nobody wants to share their data.
“We use a mixture of data,” said Kexun Zhang, head of research at startup ChipAgents, which trains AI agents to help with front-end tasks including RTL generation, design, and verification. “Some of our data is synthesized. Some is from the open-source world and some we acquired on our own. But there’s another option. We try to work with our customers to train bespoke models for them, because the amount of data that our customers have is much larger than whatever data is in the open. Also, it’s going to be more customized to their own needs. We collaborate with them and adjust our tools, including our models, to whatever customizations they want.”
How long it takes to train a model for a chip design tool depends on the specific function. “A usual time period could be one month to half a year, but that’s at the current scale of things we’re doing,” said Zhang. “It’s really a flexible number, depending on how much customization they want and how much data they’re willing to share.”
If proprietary issues can be worked out, sharing data could save money and time for everyone in the supply chain. “What you’re trying to solve is if you can model everything upfront and make it very real-time, the moment you have data that something is going in the wrong direction, you immediately tell all your suppliers, either put a halt on it or find another source,” said Sathishkumar Balasubramanian, head of products at Siemens EDA. “You immediately start giving the feedback loop and this is what we call an entire digital twin loop, all the way from what we do in a virtual world to what happens in the physical world, and how, if you can shorten that cycle with less disruption and enough shift left thinking, then you will be the first one to come up with a product that meets all the objectives and even exceeds them.”
There’s a lot of value in having different groups work together because they have different strengths, perspectives, and approaches. “That can be very, very powerful if it’s done well,” said Kepler. “But there are also challenges. One of the most basic is around data sharing; if each of the entities regards their data as being proprietary, or has to treat their data as being proprietary, for some rule that they have, then the data can’t be shared properly, and that hamstrings the whole thing. You can have really basic things, like the firewall of each company for their internal internet. Their email system might not allow outsiders. We’ve worked within our partners’ facilities and found that while we can work within the physical building, we can’t work within the IT infrastructure, because it is firewalled to all but employees.”
Chiplets add another layer of complexity to the question of IP, data, and ownership because they may come from different companies into one system. The ME Commons’ California-Pacific-Northwest AI Hardware Hub received funding for energy-efficient and scalable AI hardware systems through heterogeneous integration of specialized chiplets. But there are still many questions.
“How do I enable not just interoperability, not just greasing the skids on chiplet manufacturing, but the business model around, how do you make that financially viable?” said Nandan Nayampally, chief commercial officer at Baya Systems. “The cost structure has gotten to the point where it becomes economical to do chiplets, but the risk structure has not changed. If there’s a model that says, ‘Okay, who’s going to underwrite the risk of having three different chiplets, and we don’t know which one is bad, who takes the cost?’ It’s interesting to think about how to enable the industry to take more risks.”
IP suppliers and EDA companies must figure out a whole different way to automate and provide efficiency in the age of AI when chiplets are a reality. “The back end, the manufacturing process, wasn’t going to solve the entire problem. They just couldn’t,” said Michal Siwinski, chief marketing officer at Arteris. “You start seeing more collaboration between the EDA companies and foundries. What that basically means is that the IP, automation, EDA, and design process become much more relevant, because it’s no longer just about how you manufacture, it’s about how you design. The current AI inflection puts that even further into perspective.”
PDK and foundry access challenges for new organizations
Foundries’ process design kits are needed to enable more companies to design chips on the various manufacturing process nodes, but PDK access can be difficult.
“Foundries are a huge challenge because they are very protective of their IP,” said Vikram Bhatia, executive director, cloud product management at Synopsys. “Typically, foundries would send you PDKs or collaterals, and this is essentially the code libraries you need to complete your design before you can start manufacturing. Foundries make new organizations, or smaller organizations, go through a series of legal and security measures before they would verify you to receive their PDKs.”
Government programs, startup incubators, and EDA cloud platforms can all help gain access to PDKs faster.
“We’ve been participating in groups to try to come up with proposals to the government on how design funding would work because it’s not just the tools, but also, critically, the PDKs,” said Marc Swinnen, director of product marketing at Ansys. “A lot of that bridges the divide between whether it is a foundry thing, or a tool where the two sides meet, because the goal of the government is not just to promote research, but also to democratize chip design. Today, advanced chip design is the purview of a small number of companies with very advanced teams, and everybody else has no access to the tools, no access to the PDKs, no access to the expertise. The government wants to make tools more widely available. That’s a noble goal. It remains to be seen how exactly that can be carried out.”
When it comes to obstacles for new organizations and startups, almost everything boils down to time and access to foundry PDKs. “If it’s going to take two months to certify, two months is time you don’t have,” said Bhatia. “It’s the same thing with setting up the EDA environment itself, eight- to 12-month minimum for somebody who’s doing it from scratch, whether you do it by buying your own hardware and buying your own software licenses, or you do it on a cloud platform by picking one of the top cloud providers. The EDA environment is very complex; the networking, the storage, the overall setup, the security requirements, all of that will take several weeks to do. Everything from a challenge perspective is ultimately how much time you have and how much time you can waste on all of this stuff.”
Fig. 1: Key infrastructure needs at different levels of the stack, including PDKs and foundational circuit IP. Source: NSTC Strategic Plan 2025–2027
Measuring progress, maintaining funding
When it comes to large-scale programs, there are different time horizons for what success looks like.
“In the short term, most of the success is around new technologies coming to the market,” said Kamdar. “Can the government sponsorship, CHIPS Act, bring things faster to the market than whatever path we were on before? As a public company, profitable revenue growth is one of the metrics that we look for, but if I look at the medium-term and the longer-term perspective, it is what’s happening in the industry. Are there more PhD programs working in semiconductors? Are there more things happening for material science and research in universities? Are there more startups coming up that are going to do semiconductor design in this space? And is that pace of change faster than what we had before the CHIPS Act, where a lot of things were assumed to go to Taiwan or Japan, or some other place overseas, and does that change? I see ROI in those ways. KPIs include innovations coming to market and sustainable, profitable growth.”
One of the simplest ways to measure whether a program has achieved its goal is to calculate the time from concept to prototype. “This is a metric that we can use to measure the typical number of quarters to get to the successful prototype,” said Prasad. “Then we are going to actively measure how we are removing some of the bottlenecks along the way, and not only saving on time, but also saving on the amount of idle headcount dollars that are spent when you are waiting for certain next milestones to become available for you to act. In addition, we have our research metrics and our workforce development metrics. The NSTC–UCLA program did 230 tape-outs this year. They are supporting 1,000 classroom tape-outs next year. They are training new professors in 23 universities on tape-out classes, so that kind of exponential growth is what we want.”
Fig. 2: Example journey of commercializing a research idea using NSTC offerings. Source: NSTC Strategic Plan 2025–2027
Prasad noted a key difference between government services such as the Small Business Innovation Research (SBIR) program and newer funding initiatives. “When you look at the DARPA program or even the NSTC Research Program, they are spending the money that is allocated, but the whole support ecosystem is supposed to be a self-sustaining enterprise that we are creating, and that’s why it is not created as a government program. It’s created as a non-profit startup that will allow us to create a lasting enterprise out of them for 10 years.”
With any of these types of investments, eventually the initial investment will go away, yet the project may need 10 years to stand up the technology capability, observed Booz Allen’s Fazzari. “How do we sustain this in such a way that it’s meaningful to this community, where the investments that were put into it, and the fact that the vendors are willing to participate, they continue that relationship and the funding model works its way out in a way that makes sense?”
Fazzari does not think the government is going to keep handing out billions of dollars. “I don’t see in the current administration and environment that you’re going to see another — whatever the number might be — dropped into this space when they’re saying, ‘Foreign companies are investing $100 billion into the US.’ It needs to be a collective to go after this in a way that says we’re ready. We’re going to be aggressive about making it happen.”
Conclusion
Overall, collaboration between government, industry, and academia seems the best way to solve design bottlenecks and train a future workforce that will eventually be not only digital native but AI native.
A key achievement of the CHIPS Act and ME Commons is that it brought design to the forefront with concepts like lab-to-fab. “It’s forced the community to rethink, how do we deal with EDA?” said Fazzari. “Within any Commons, they stood up an ecosystem to allow for access, but more importantly, it’s getting people to think about what this means from there, and how we start creating IP for innovation. In the past, there have been situations where you’ve developed this technology, but how do you bring it consistently forward?”
One idea is to grow the ME Commons hub concept. “A lot of the initial thought process was how to help with the workforce: How do we help students learn about design techniques? How do we give them access to EDA and EDA tools?” said Keysight’s Kamdar. “That was all done as part of the first year, and now we can move into more detailed work. Now it’s, if they do have designs, can we set something up so they get access to the foundry capacity, and they can build something? Then, can they also get access to some kind of lab where they would be able to do measurements on their chip, so that they can prove the performance of the chip, or that they know the chip performs? The chip was built and designed in a certain way, and now they’re seeing the results match up to what they designed. There are lots of different ways in which this can be expanded.”
References
[1] DAC 62 panel: “Design, Develop, Dominate: The CHIPS Act’s Role in Semiconductor Innovation.”
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