tag: ANSYS

A High-Capacity Solution for Power and Signal Integrity on 2.5D Silicon Interposers
By Ansys - 12 Jun, 2024 - Comments: 0

The present trends in technology — such as increasing demand for computational power from CPUs and GPUs, connectivity driven by Internet of Things (IoT), data demands around connected and self-driving cars, and the design of processors optimized for artificial intelligence (AI) — require more functionality from integrated circuits. As designers struggle to find ways to scale with complexity... » read more

Blog Review: June 12
By Jesse Allen - 12 Jun, 2024 - Comments: 0

Cadence's Deep Mehta finds that PCIe 6.0 switches need advanced verification strategies that delve deeper than basic functionality, such as generating backpressure traffic to identify potential performance bottlenecks and ensure the switch operates optimally in real-world scenarios. Siemens' Reetika explains why proper management and verification of reset domain crossing (RDC) paths are cruc... » read more

Toward A Software-Defined Hardware World
By Karen Heyman - 06 Jun, 2024 - Comments: 0

Software-defined hardware may be the ultimate Shift Left approach as chip design grows closer to true co-design than ever with potential capacity baked into the hardware, and greater functionality delivered over the air or via a software update. This marks another advance in the quest for lower power, one that’s so revolutionary that it’s upending traditional ideas about model-based systems... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh provides an overview of the low power entry and exit flows in USB4 Version 2.0 link speed and how they have been simplified by making low power entry uni-directional and removing the need for certain handshakes for low power exit of the re-timers. In a podcast, Siemens' Steph Chavez chats with Daniel Beeker of NXP about the foundational importance of power distributio... » read more

Physics-Aware AI Is The Key To Next Gen IC Design
By Marc Swinnen - 03 Jun, 2024 - Comments: 0

Chip design projects are notorious for generating huge amounts of design data. The design process calls for a dozen or more electronic design automation (EDA) software tools to be run in sequence. Together, they write out hundreds of gigabytes of intermediate data on the way to creating a final layout for manufacturing. Traditionally, this has been seen as a problem. But this richness of data i... » read more

Chip Industry Week In Review
By The SE Staff - 31 May, 2024 - Comments: 0

JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Chip Industry Week In Review
By The SE Staff - 24 May, 2024 - Comments: 0

Absolics, an affiliate of Korea materials company SKC, will receive up to $75 million in direct funding under the U.S. CHIPS Act for the construction of a 120,000 square-foot facility in Covington, Georgia, for glass substrates in advanced packaging. imec will host a €2.5 billion (~$2.72B) pilot line for researching chips beyond 2nm, partially funded through the EU Chips Act. imec CEO Luc ... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Chip Aging Becoming Key Factor In Data Center Economics
By Ann Mutschler - 20 May, 2024 - Comments: 1

Chip aging is becoming a much bigger concern inside of data centers, where it can impact server uptime, utilization rates, and the amount of energy needed to drive signals and cool entire server racks. Aging in chips is the result of both higher logic utilization and increasing transistor density. This is problematic for data centers, in general, but especially for AI chips where digital log... » read more

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